Patents by Inventor Yung Lin

Yung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240165233
    Abstract: The present invention relates to a method for reducing localized fat deposits in a subject in need thereof in need thereof by topically treating the subject with rare-earth element doped calcium carbonate particles in combination with low-intensity ultrasound. The rare-earth element doped calcium carbonate particles have good biocompatibility and can increase reactive oxygen species (ROS) production and produce carbon dioxide (CO2) and calcium ions (Ca2+) in the region of administration under the ultrasonic irradiation. The method of the present invention is effective in inducing adipocyte necrosis, inhibiting adipogenesis, and decreasing body weight and useful for body sculpture.
    Type: Application
    Filed: November 17, 2022
    Publication date: May 23, 2024
    Applicants: National Health Research Institutes, National United University, National Taiwan University
    Inventors: Feng-Huei LIN, Gin-Shin CHEN, Ping-Yu SHIH, Ching-Yun CHEN, Li-Ze LIN, Che-Yung KUAN, Zhi-Yu CHEN, I-Hsuan YANG
  • Publication number: 20240162356
    Abstract: A light detecting device includes a substrate that has a lattice constant. A buffer layer is disposed on the substrate. A gradient layer is formed on the buffer layer opposite to the substrate, and includes a plurality of sublayers that have respectively lattice constants each of which is greater than the lattice constant of the substrate. The sublayers are arranged in a manner that the lattice constants of the sublayers undergo a gradual increase in lattice constant in a direction away from the substrate. A barrier layer is formed on the gradient layer opposite to the buffer layer, and has a lattice constant which is greater than that of the substrate and no smaller than the lattice constants of the sublayers. An absorption layer is formed on the barrier layer opposite to the gradient layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: May 16, 2024
    Inventors: Hung-Wen HUANG, Yung-Chao CHEN, Yi-Hsiang WANG, Wei LIN
  • Publication number: 20240163988
    Abstract: A controller for controlling a light source module including a first LED array and a second LED array includes a first driving terminal and a second driving terminal. The controller is operable for turning on a switch between a power converter and the first LED array by the first driving terminal to deliver electric power from the power converter to the first LED array in a first sequence of discrete time slots, and for turning on a second switch between the power converter and the second LED array by the second driving terminal to deliver electric power from the power converter to the second LED array in a second sequence of discrete time slots, where the first sequence of discrete time slots and the second sequence of discrete time slots are mutually exclusive.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Inventors: Rong HU, Yung-Lin LIN, Naoyuki FUJITA
  • Publication number: 20240153895
    Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.
    Type: Application
    Filed: April 19, 2023
    Publication date: May 9, 2024
    Inventors: Harry-HakLay CHUANG, Wei-Cheng WU, Chung-Jen HUANG, Yung Chun TU, Chien Lin LIU, Shun-Kuan LIN, Ping-tzu CHEN
  • Publication number: 20240155843
    Abstract: A semiconductor device includes a substrate having a flash memory region and a logic device region, a logic transistor disposed in the logic device region, and a flash memory transistor disposed in the flash memory region. The flash memory transistor includes a metal select gate having two opposite sidewalls and two memory gates disposed on the two opposite sidewalls of the metal select gate.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 9, 2024
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wang Xiang, CHIA CHING HSU, Shen-De Wang, Yung-Lin Tseng, WEICHANG LIU
  • Patent number: 11977655
    Abstract: A computer-implemented method, a computer system, and computer program product for associating security events. The method includes obtaining a result of implementation of one or more Locality-Sensitive Hashing (LSH) functions to feature data of a first event detected by a first device. The method also includes mapping the result to one or more positions in a data structure. In response to data elements of the one or more positions indicating first information associating with the one or more positions exists in a storage, the method includes obtaining the first information from the storage. The method further includes sending the first information to the first device.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: May 7, 2024
    Assignee: International Business Machines Corporation
    Inventors: Jia-Sian Jhang, Chen-Yu Kuo, Hsiao-Yung Chen, Lu Cheng Lin, Chien Wen Jung
  • Publication number: 20240146205
    Abstract: A flyback power converter includes a power transformer, a first lossless voltage conversion circuit, a first low-dropout linear regulator and a secondary side power supply circuit. The first low-dropout linear regulator (LDO) generates a first operation voltage as power supply for being supplied to a sub-operation circuit. The secondary side power supply circuit includes a second lossless voltage conversion circuit and a second LDO. The second LDO generates a second operation voltage. The first operation voltage and the second operation voltage are shunted to a common node. When a first lossless conversion voltage is greater than a first threshold voltage, the second LDO is enabled to generate the second operation voltage to replace the first operation voltage as power supply supplied to the sub-operation circuit; wherein the second lossless conversion voltage is lower than the first lossless switching voltage.
    Type: Application
    Filed: September 23, 2023
    Publication date: May 2, 2024
    Inventors: Shin-Li Lin, He-Yi Shu, Shih-Jen Yang, Ta-Yung Yang, Yi-Min Shiu, Chih-Ching Lee, Yu-Chieh Hsieh, Chao-Chi Chen
  • Publication number: 20240144467
    Abstract: A hot spot defect detecting method and a hot spot defect detecting system are provided. In the method, hot spots are extracted from a design of a semiconductor product to define a hot spot map comprising hot spot groups, wherein local patterns in a same context of the design yielding a same image content are defined as a same hot spot group. During runtime, defect images obtained by an inspection tool performing hot scans on a wafer manufactured with the design are acquired and the hot spot map is aligned to each defect image to locate the hot spot groups. The hot spot defects in each defect image are detected by dynamically mapping the hot spot groups located in each defect image to a plurality of threshold regions and respectively performing automatic thresholding on pixel values of the hot spots of each hot spot group in the corresponding threshold region.
    Type: Application
    Filed: January 8, 2024
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Huei Chen, Pei-Chao Su, Xiaomeng Chen, Chan-Ming Chang, Shih-Yung Chen, Hung-Yi Chung, Kuang-Shing Chen, Li-Jou Lee, Yung-Cheng Lin, Wei-Chen Wu, Shih-Chang Wang, Chien-An Lin
  • Patent number: 11973261
    Abstract: An antenna structure with wide radiation bandwidth in a reduced physical space includes a metallic housing, a first feed portion, and a second feed portion. The metallic housing includes a metallic side frame and a metallic back board. The metallic side frame defines a slot, and first and second gaps. The metallic side frame between the first gap and one end of the slot forms a first radiation portion. The second gap divides the first radiation portion into first and second radiation sections. The first feed portion feeds current and signal to the first radiation section, and the first radiation section works in a GPS mode and a WIFI 2.4 GHz mode. The second feed portion feeds current and signal to the second radiation section, and the second radiation section works in a WIFI 5 GHz mode.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 30, 2024
    Assignee: Chiun Mai Communication Systems, Inc.
    Inventors: Kun-Lin Sung, Yung-Chin Chen, Yi-Chieh Lee
  • Publication number: 20240136213
    Abstract: In an embodiment, a system, includes: a first pressurized load port interfaced with a workstation body; a second pressurized load port interfaced with the workstation body; the workstation body maintained at a set pressure level, wherein the workstation body comprises an internal material handling system configured to move a semiconductor workpiece within the workstation body between the first and second pressurized load ports at the set pressure level; a first modular tool interfaced with the first pressurized load port, wherein the first modular tool is configured to process the semiconductor workpiece; and a second modular tool interfaced with the second pressurized load port, wherein the second modular tool is configured to inspect the semiconductor workpiece processed by the first modular tool.
    Type: Application
    Filed: January 3, 2024
    Publication date: April 25, 2024
    Inventors: Chun-Jung HUANG, Yung-Lin HSU, Kuang Huan HSU, Jeff CHEN, Steven HUANG, Yueh-Lun YANG
  • Patent number: 11965259
    Abstract: An integrated hydrogen gas generator with hydrogen water module comprises a water tank, an electrolytic module, an integrated flow channel device, a humidifying module, and a hydrogen water module. The electrolytic module is configured to electrolyze the water in the water tank to generate a gas comprising hydrogen. The water tank, the humidifying module, and the hydrogen water module are respectively coupled to the integrated passageway module so that the water and the gas comprising hydrogen flow in a special sequence between them. The humidifying module is configured to humidify the gas comprising hydrogen. The hydrogen water module is configured for accommodating liquid and receiving the gas comprising hydrogen into the liquid to form a liquid comprising hydrogen. The configuration of pipeline is replaced by the integrated passageway module in the integrated hydrogen gas generator of the present invention.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: April 23, 2024
    Assignee: Shanghai Asclepius Meditec Co., Ltd.
    Inventor: Hsin-Yung Lin
  • Patent number: 11967532
    Abstract: A method of forming a semiconductor structure includes forming a semiconductor fin over a substrate, forming a dummy gate stack over the semiconductor fin, depositing a dielectric layer over the dummy gate stack, and selectively etching the dielectric layer, such that a top portion and a bottom portion of the dielectric layer form a step profile. The method further includes removing portions of the dielectric layer to form a gate spacer and subsequently forming a source/drain feature in the semiconductor fin adjacent to the gate spacer.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 23, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Chih-Yung Lin, Jhon Jhy Liaw
  • Publication number: 20240126327
    Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chao Wei LIU, Wei-Hao CHANG, Yung-I YEH, Jen-Chieh KAO, Tun-Ching PI, Ming-Hung CHEN, Hui-Ping JIAN, Shang-Lin WU
  • Publication number: 20240128876
    Abstract: A switching control circuit for use in controlling a resonant flyback power converter generates a first driving signal and a second driving signal. The first driving signal is configured to turn on the first transistor to generate a first current to magnetize a transformer and charge a resonant capacitor. The transformer and charge a resonant capacitor are connected in series. The second driving signal is configured to turn on the second transistor to generate a second current to discharge the resonant capacitor. During a power-on period of the resonant flyback power converter, the second driving signal includes a plurality of short-pulses configured to turn on the second transistor for discharging the resonant capacitor. A pulse-width of the short-pulses of the second driving signal is short to an extent that the second current does not exceed a current limit threshold.
    Type: Application
    Filed: June 15, 2023
    Publication date: April 18, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Fu-Ciao Syu, Chia-Hsien Yang, Hsin-Yi Wu
  • Patent number: 11961884
    Abstract: The present disclosure describes a semiconductor device with a fill structure. The semiconductor structure includes first and second fin structures on a substrate, an isolation region on the substrate and between the first and second fin structures, a first gate structure disposed on the first fin structure and the isolation region, a second gate structure disposed on the second fin structure and the isolation region, and the fill structure on the isolation region and between the first and second gate structures. The fill structure includes a dielectric structure between the first and second gate structures and an air gap enclosed by the dielectric structure. The air gap is below top surfaces of the first and second fin structures.
    Type: Grant
    Filed: December 13, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiu-Yung Lin, Yen Chuang, Min-Hao Hong
  • Publication number: 20240120900
    Abstract: A suspended resonator including a vibration structure, a first electrode, and a second electrode is provided. The vibration structure includes a vibration region, a frame portion, and a connecting portion. The vibration region includes a plate portion and a thickening portion. The plate portion has a first surface and a second surface opposite to each other. The thickening portion surrounds a central part of the plate portion, and an edge part of the plate portion is sandwiched in the thickening portion. A thickness of the thickening portion is greater than a thickness of the plate portion. The frame portion surrounds the vibration region and maintains a gap with the vibration region. The connecting portion connects the thickening portion with the frame portion. The first electrode is disposed on the first surface. The second electrode is disposed on the second surface.
    Type: Application
    Filed: February 2, 2023
    Publication date: April 11, 2024
    Applicant: TXC Corporation
    Inventors: Shih-Yung Pao, Tzu-Hsiu Peng, Zong-De Lin
  • Publication number: 20240120846
    Abstract: A resonant flyback power converter includes: a first transistor and a second transistor which are configured to switch a transformer and a resonant capacitor for generating an output voltage; and a switching control circuit generating first and second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal magnetizes the transformer. During a DCM (discontinuous conduction mode) operation, the second driving signal includes a resonant pulse for demagnetizing the transformer and a ZVS (zero voltage switching) pulse for achieving ZVS of the first transistor. The resonant pulse is skipped when the output voltage is lower than a low-voltage threshold.
    Type: Application
    Filed: April 14, 2023
    Publication date: April 11, 2024
    Inventors: Yu-Chang Chen, Ta-Yung Yang, Kun-Yu Lin, Hsin-Yi Wu
  • Publication number: 20240120844
    Abstract: A resonant flyback power converter includes: a first and a second transistors which form a half-bridge circuit for switching a transformer and a resonant capacitor to generate an output voltage; a current-sense device for sensing a switching current of the half-bridge circuit to generate a current-sense signal; and a switching control circuit generating a first and a second driving signals for controlling the first and the second transistors. The turn-on of the first driving signal controls the half-bridge circuit to generate a positive current to magnetize the transformer and charge the resonant capacitor. The turn-on of the second driving signal controls the half-bridge circuit to generate a negative current to discharge the resonant capacitor. The switching control circuit turns off the first transistor when the positive current exceeds a positive-over-current threshold, and/or, turns off the second transistor when the negative current exceeds a negative-over-current threshold.
    Type: Application
    Filed: April 10, 2023
    Publication date: April 11, 2024
    Inventors: Kun-Yu LIN, Ta-Yung YANG, Yu-Chang CHEN, Hsin-Yi WU, Fu-Ciao SYU, Chia-Hsien YANG
  • Patent number: D1022903
    Type: Grant
    Filed: July 13, 2022
    Date of Patent: April 16, 2024
    Inventor: Hsin-Yung Lin
  • Patent number: D1026166
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 7, 2024
    Inventor: Hsin-Yung Lin