Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: Provided is a word line structure including a substrate, a stack structure, and a metal silicide structure. The stack structure is disposed on the substrate. The metal silicide structure is disposed on the stack structure. The metal silicide structure includes a first metal element, a second metal element, and a silicon element. The first metal element is different from the second metal element, and concentrations of the first metal element and the second metal element gradually decrease along a direction from a top surface of the metal silicide structure to the substrate.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: An integrated circuit includes a stack in a stack region and a region outside the stack region. A buttress structure disposed outside the stack includes a fence-shaped, electrically passive element configured to oppose expansion of materials outside the stack region in a direction toward the stack region.

Abstract: An integrated circuit includes a multilayer stack, and a plurality of layered conductors extending in the multilayer stack and into a conductor layer beneath the multilayer stack. The layered conductor has a bottom conductor layer in ohmic electrical contact with the conductive layer in a substrate, an intermediate conductive liner layer over the bottom conductor layer and lining a portion of sidewall of the corresponding trench, and a top conductor layer on the top conductive liner layer.

Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.

Abstract: A method of forming a conductive plug is disclosed. A material layer having at least one opening is provided on a substrate. A first conductive layer is deposited in the opening, wherein the first conductive layer does not completely fill up the opening. A second conductive layer is deposited on the first conductive layer. A surface treatment is performed after the step of depositing the first conductive layer and before the step of depositing the second conductive layer, so that the first deposition rate of the second conductive layer at the lower portion of the opening is greater the second deposition rate of the second conductive layer at the upper portion of the opening. A void-free conductive plug can be easily formed with the method of the invention.

Abstract: A semiconductor device is provided, which includes a first conductive layer disposed on a substrate, a dielectric layer with at least an opening disposed on the first conductive layer, and a plurality of plugs filling up the openings. At least a portion of the dielectric layer adjacent to the openings is Si-rich, and each of the plugs includes a second conductive layer surrounded by a barrier layer.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure comprises a conductive layer, a via, and a barrier layer disposed between the conductive layer and the via. The barrier layer is stuffed with oxygen.

Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. Thereafter, a dielectric layer is formed on the substrate, wherein the dielectric layer includes a first portion adjacent to the substrate and a second portion adjacent to the first portion. Afterwards, the dielectric layer is treated with nitrogen trifluoride (NF3) to remove the second portion of the dielectric layer and therefore expose the first portion of the dielectric layer. A semiconductor device is also provided.

Abstract: A method of fabricating a semiconductor device is provided. A substrate is provided. Thereafter, a dielectric layer is formed on the substrate, wherein the dielectric layer includes a first portion adjacent to the substrate and a second portion adjacent to the first portion. Afterwards, the dielectric layer is treated with nitrogen trifluoride (NF3) to remove the second portion of the dielectric layer and therefore expose the first portion of the dielectric layer. A semiconductor device is also provided.

Abstract: A system is provided that includes a power supply connectable to a semiconductor wafer including opposing, major front and back surfaces joined by a circumferential side, with the wafer undergoing processing including electroplating a damascene layer on the wafer. The system also includes an arrangement configured to apply a polymer coating to the side of the wafer before electroplating the damascene layer, with the system being configured to apply the polymer coating in accordance with an electrophoresis technique driven by the power supply. In this regard, the polymer coating is applied to the side but not at least a portion of the front and back surfaces of the wafer, and the polymer coating provides a barrier to formation of the damascene layer on the side of the wafer.

Abstract: A semiconductor device includes a substrate having a first and second region, a first structure and a second structure. The first structure is formed over the substrate in the first region. The first structure has a first height. The second structure is formed over the substrate in the second region. The second structure has a second height different from the first height.

Abstract: A semiconductor processing apparatus includes a process chamber, a pedestal and a showerhead. The pedestal is inside the process chamber and holds a semiconductor wafer. The showerhead supplies process gas to the process chamber.

Abstract: Closed loop control may be used to improve uniformity of contact or via critical dimension using chemical mechanical planarization. For example, real-time closed loop control may be used to adjust oxide buffing or over-polishing time in a chemical mechanical planarization process to more uniformly and consistently achieve a target critical dimension of a semiconductor wafer.

Abstract: A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.