Abstract: Provided are a transistor and a manufacturing method thereof. The transistor includes a substrate, a collector, a base, an emitter and a diffusion barrier layer. The collector is disposed on the substrate. The base is disposed on the collector. The emitter is disposed on the base. The diffusion barrier layer is disposed between the base and the emitter. An upper portion of the base includes a doped layer, and the diffusion barrier layer is disposed on the doped layer. The emitter, the doped layer, and the collector are of a first conductive type, and the rest of the base is of a second conductive type.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.

Abstract: A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

Abstract: A manufacturing method of a semiconductor device includes forming a plurality of flash memory structures on a semiconductor substrate, wherein each of the flash memory structures includes a floating gate formed on the semiconductor substrate and a control gate formed on the floating gate; forming at least one pseudo contact between the plurality of flash memory structures; forming a liner film conformally on a surface of the pseudo contact; forming an interlayer dielectric layer on the whole semiconductor substrate to cover the pseudo contact and form at least one air gap between the pseudo contact and the flash memory structure; planarizing the interlayer dielectric layer until the top of the pseudo contact is exposed; removing the pseudo contact to form a contact opening; and forming a conductive material in the contact opening.

Abstract: Provided is a semiconductor device including a substrate, an isolation structure, a barrier structure, a first conductive layer, a second conductive layer, a first gate dielectric layer, and a second gate dielectric layer. The substrate has a first region and a second region. The barrier structure is located on the isolation structure. The first conductive layer is located on the first region. The second conductive layer is located on the second region. The first gate dielectric layer is located between the first conductive layer and the substrate in the first region. The second gate dielectric layer is located between the second conductive layer and the substrate in the second region. The first gate dielectric layer and the second gate dielectric layer are separated by the isolation structure. A method of manufacturing the semiconductor device is also provided.