Abstract: In general, in one aspect, the disclosure describes assigning a flow of network packets to a thread of a multi-threaded processor core in a set of multiple multi-threaded processor cores integrated on a single die. Based on the assigning, a packet in the flow is processed by the assigned processor core thread.

Abstract: A synchronous detection and calibration system is provided for expedient calibration of differential acoustic sensors in a manufacturing and testing environment. By processing a series of sequentially received tones, respective portions of a system using differential acoustic sensors are tuned for optimum individual operation, following which corresponding control data are generated and stored for use in selecting among predetermined calibration vectors which establish and maintain optimum system operation.

Abstract: In general, in one aspect, the disclosure describes a method that includes accessing a first Internet Protocol datagram comprising a first Transmission Control Protocol segment representing a connection open request, determining a first hash result based, at least in part, on the Internet Protocol source and destination addresses of the Internet Protocol datagram, and the source and destination port numbers of the first Transmission Control Protocol segment. The method also includes accessing a first bucket of array elements from a first array based on at least a portion of the determined hash result where different array elements correspond to different respective open requests. The method also includes storing an entry for the open request in an array element of the bucket.

Abstract: In general, in one aspect, the disclosure describes assigning a flow of network packets to a thread of a multi-threaded processor core in a set of multiple multi-threaded processor cores integrated on a single die. Based on the assigning, a packet in the flow is processed by the assigned processor core thread.

Abstract: A mechanism is provided to receive out-of-order packets and to use a table to place the out-of-order packets in a queue so that the packets are queued in order of a sequence in which the packets were sent.

Abstract: A timer is installed by writing a status bit into a first table indexed by a first pointer, and writing a value corresponding to timer information into a second table indexed by the first pointer.