Abstract: The method of forming the semiconductor structure comprises operations of: forming a substrate, and forming active regions located above the substrate and arranged at intervals in a first direction parallel to a top face of the substrate; and performing a modifying treatment to a part of the substrate below the active regions from at least one side face of the substrate, to form bit lines each of which extends in the first direction and is electrically connected with a plurality of the active regions arranged at intervals in the first direction

Abstract: A method for manufacturing a semiconductor structure includes providing a substrate; forming mutually parallel first trenches extending along a first direction in the substrate and first isolation structures filling the first trenches; forming mutually parallel second trenches extending along a second direction in the substrate and in the first isolation structures, the first and second trenches dividing the substrate to form active pillars, and a depth of the second trenches being less than that of the first trenches; forming second isolation structures alternately arranged with the first isolation structures along the second direction at bottoms of the second trenches, top surfaces of the second isolation structures being lower than bottom surfaces of the second trenches located in the first isolation structures; forming bit line structures on the second isolation structures; and forming word line structures above the bit line structures.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base including a first region and a second region, where a plurality of active pillars are arranged at intervals in the base located in the first region; forming a first dielectric layer on the base, where the first dielectric layer covers the plurality of active pillars; forming a first mask layer with a first mask pattern on the first dielectric layer; forming a second mask layer with a second mask pattern on the first mask layer; forming a third mask layer with a third mask opening, where the third mask opening is used to expose the first region; and removing part of the first dielectric layer by using the first mask layer, the second mask layer, and the third mask layer as a mask.

Abstract: Embodiments relate to a semiconductor structure and a fabrication method thereof The method for fabricating a semiconductor structure includes: providing a substrate, where a semiconductor stacked structure formed by alternately stacking first semiconductor layers and second semiconductor layers is formed on the substrate; patterning the semiconductor stacked structure to form cell structures extending along a first direction and arranged at intervals; removing a part of the first semiconductor layers positioned in first regions in the cell structures, such that a part of the second semiconductor layers positioned in the first regions form capacitor support structures; and forming capacitors on exposed surfaces of the capacitor support structures, where the capacitors include first electrodes, dielectric layers and second electrodes sequentially stacked along a direction distant from the capacitor support structures; and all the capacitors in the first regions share the same second electrode.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes a substrate, a plurality of active pillars arranged above the substrate, a storage structure, and a plurality of transistors. The active pillars are arranged in an array in a first direction and in a second direction. Each active pillar includes a first sub active pillar and a second sub active pillar arranged on the first sub active pillar. The first direction and the second direction intersect with each other and are both parallel to a top surface of the substrate. A material of the first sub active pillar includes a first element, and resistivity of the first sub active pillar including the first element is less than resistivity of the first sub active pillar absence of the first element. The storage structure covers a sidewall of the first sub active pillar.

Abstract: Embodiments relate to a semiconductor structure and a formation method. The method includes: providing a base substrate, where the base substrate includes a substrate and an insulating material layer, the substrate includes a plurality of first trenches arranged at intervals along a first direction, and the insulating material layer fills each of the plurality of first trenches; etching the base substrate to form a plurality of second trenches arranged at intervals along a second direction, the second direction intersecting the first direction; removing a part of a material of the substrate below the plurality of second trenches to form third trenches below the plurality of second trenches, the third trenches penetrating through each of the plurality of second trenches; filling a conductive material into the third trenches to form bit line structures; and forming word line structures in the plurality of second trenches.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of memory cells located on a substrate. Each of the plurality of memory cells includes a transistor and a capacitor. The capacitor is electrically connected to the transistor. The capacitor includes a body portion, and at least one extension portion located on a side surface of the body portion, and the at least one extension portion is electrically connected to the body portion.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, including a semiconductor substrate, the semiconductor substrate is provided with first trenches extending along a first direction and second trenches extending along a second direction, the first trenches intersect with the second trenches to form a plurality of semiconductor pillars on the semiconductor substrate, the second trench is filled with a first dielectric layer, a second dielectric layer is provided on a top of the semiconductor pillar, and a third dielectric layer is provided on a sidewall of the first trench; an isolation layer, located in the semiconductor substrate below the first trenches and extending along the second direction; and a bit line, located on a surface of the isolation layer and extending along the second direction, the bit line is connected to a bottom of the semiconductor pillar.

Abstract: Provided is a semiconductor structure, a test structure, a manufacturing method and a test method. The semiconductor structure includes a substrate, which includes multiple pillars spaced along a first direction by first trenches; second trenches formed at opposite sides along a second direction of each of the pillars; target conductive structures extending along the second direction in the substrate directly below adjacent second trenches; and a first dielectric layer, a conductive layer and a second dielectric layer sequentially stacked in the first trenches and the second trenches. A depth of the first trenches is greater than that of the second trenches. The first direction intersects the second direction.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, where the substrate includes first grooves arranged at intervals therein along a first direction and a filling layer in the first groove; patterning the substrate, to form second grooves, where the second groove is located on a top surface of the first groove, forming a protective layer on a surface of the substrate, where the protective layer is different from the filling layer; forming a bit line structure at a bottom of the second groove; forming a first isolation layer, where the first isolation layer is located in the second groove and on a top surface of the bit line structure; partially removing the filling layer, where the retained filling layer is flush with an upper surface of the first isolation layer.

Abstract: A method for forming a three-dimensional memory provided by embodiments includes: forming a substrate and a stacked layer, where the stacked layer includes first semiconductor layers and second semiconductor layers alternately stacked, a thickness of the second semiconductor layers is D1, the first semiconductor layers include a plurality of channel regions as well as a first region and a second region arranged on opposite two sides of each of the plurality of channel regions along a first direction, and the first direction is a direction parallel to the top surface of the substrate; forming a plurality of first openings respectively exposing the plurality of channel regions, a gap between adjacent two of the plurality of first openings along a second direction has a width D2, D1>D2; and depositing a conductive layer along the plurality of first openings.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a laminate structure arranged on the substrate and including first semiconductor layers spaced apart from each other in a direction perpendicular to a top surface of the substrate, each first semiconductor layer including channel areas spaced apart from each other in a first direction, and first doped areas and second doped areas, each first doped area being arranged on one side of a respective one of the channel areas in a second direction, each second doped area being arranged on another side of the respective one of the channel areas in the second direction; and a word line structure including word lines extending in the first direction, an edge of each word line being flush with en edge of a respective one of the channel areas in the second direction.

Abstract: The present disclosure relates to a semiconductor structure and a manufacturing method thereof. The method of manufacturing a semiconductor structure includes: providing a base; forming a plurality of first trenches arranged in parallel at intervals and extending along a first direction, and an initial active region between two adjacent ones of the first trenches, wherein the initial active region includes a first initial source-drain region close to a bottom of the first trench, a second initial source-drain region away from the bottom of the first trench, and an initial channel region located between the first initial source-drain region and the second initial source-drain region; forming a protective dielectric layer, wherein the protective dielectric layer covers a sidewall of the second initial source-drain region and a sidewall of the initial channel region; thinning the first initial source-drain region.

Abstract: Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure, relating to the field of semiconductor technology. The semiconductor structure includes a substrate, a capacitor structure, a transistor structure, a bit line and a word line; and the substrate includes a semiconductor layer and a spacer. The capacitor structure is arranged on the substrate, and the spacer is positioned between the capacitor structure and at least a part of the semiconductor layer. The transistor structure and the word line are arranged on a side of the capacitor structure distant from the substrate, one of a source and a drain of the transistor structure is electrically connected to the capacitor structure, a gate of the transistor structure is electrically connected to the word line, and other one of the source and the drain of the transistor structure is electrically connected to the bit line.

Abstract: The present disclosure provides a semiconductor structure and a manufacturing method thereof, relates to the technical field of semiconductors. The manufacturing method includes: forming a plurality of first trenches arranged at intervals and extending along a first direction in a base; forming a first insulating layer on a sidewall of the first trench, where a thickness of the first insulating layer is smaller than a target value, and the first insulating layer defines a second trench; performing a silicification reaction on a substrate exposed in the second trench; forming a second insulating layer on a sidewall of the second trench, where the second insulating layer defines a third trench, and a sum of thicknesses of the first insulating layer and the second insulating layer is equal to the target value; and forming an isolation layer in the third trench.

Abstract: The present disclosure relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor device and a forming method thereof. The forming method of a semiconductor device includes: providing a substrate; etching the substrate to form first recesses and second recesses located below the first recesses and communicating with the first recesses; forming a bit line in the second recesses; forming, at bottoms of the first recesses, an isolation layer covering the bit line; enlarging an inner diameter of the first recess above the isolation layer; and forming a gate layer on a sidewall of the first recess whose inner diameter is enlarged.

Abstract: A semiconductor structure includes at least one transistor. The transistor includes a channel, a gate, a source, and a drain. The channel includes a first material layer and a second material layer arranged around the first material layer. Resistivity of the first material layer is greater than a first preset value, and resistivity of the second material layer is less than a second preset value, the first preset value being greater than the second preset value. The gate covers at least one side of the channel. The source and the drain are at two ends of an extension direction of the channel.

Abstract: Embodiments relate to a semiconductor structure, and an array structure and a method for fabricating same. The semiconductor structure includes: a substrate having a bit line structure therein; an active area, where an end of the active area is positioned on the bit line structure, and along a direction perpendicular to the substrate, the active area includes a first channel layer and a second channel layer wrapping at least a bottom surface and part of a sidewall of the first channel layer, and a bottom of the second channel layer is electrically connected to the bit line structure; a word line structure, where the word line structure is positioned on two opposite sides of the active area in the direction perpendicular to the substrate; and a source and a drain respectively positioned at two ends along an extension direction of the active area.

Abstract: A method for manufacturing a semiconductor structure includes: forming first shallow trench isolation structures in a substrate, which isolate a plurality of active areas extending in first direction in the substrate, in which a first shallow trench isolation structure includes a sacrificial layer and a first dielectric layer stacked from bottom up in sequence; forming a plurality of word line isolation grooves in the substrate, in which a word line isolation groove is located above the sacrificial layer and extends in second direction; forming a second dielectric layer on sidewalls of the word line isolation groove, in which a pore penetrating to the substrate is provided inside the second dielectric layer; metallizing a lower part of an active area based on the pore to form a bit line extending in first direction; and removing the sacrificial layer based on the pore to form an air gap between adjacent bit lines.