Patents by Inventor Yuri Kato

Yuri Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171872
    Abstract: A solid state imaging device comprises a pixel array that comprises a plurality of imaging pixels, each of which being capable to generate an imaging signal depending on the intensity of light falling on the imaging pixel, and to detect as an event a positive or negative change of light intensity that is larger than a respective predetermined threshold, and a control unit that is configured to count the number of events occurring within at least one group of imaging pixels and to read out the imaging signals of the imaging pixels within one of the groups, if the according counted number of events is larger than or equal to a predetermined readout threshold.
    Type: Application
    Filed: March 24, 2022
    Publication date: May 23, 2024
    Applicant: Sony Semiconductor Solutions Corporation
    Inventors: Mojdeh MOHAJERANI, Christian Peter BRÄNDLI, Yuri KATO
  • Publication number: 20240036096
    Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 1, 2024
    Inventors: JUN OGI, YURI KATO, NAOHIKO KIMIZUKA, YOSHIHISA MATOBA, KAN SHIMIZU
  • Publication number: 20240002343
    Abstract: The present invention provides a compound for treating or preventing diseases caused by mitochondrial hyperfission. The present invention provides a compound represented by formula (1): wherein R1 and R1? are each independently hydrogen, an optionally substituted lower alkyl, an optionally substituted lower cycloalkyl, and the like; R2 is an optionally substituted lower alkyl, an optionally substituted lower cycloalkyl, and the like; R3 and R4 are each independently hydrogen, halogen, hydroxy, nitro, cyano, an optionally substituted lower alkyl, and the like; R5 and R6 are each independently an optionally substituted lower alkyl; an optionally substituted lower cycloalkyl, and the like; X is nitrogen or oxygen; Y is carbon, nitrogen or oxygen; and a broken line represents the presence or absence of a bond; or a pharmaceutically acceptable salt, a solvate, or a prodrug thereof.
    Type: Application
    Filed: November 29, 2021
    Publication date: January 4, 2024
    Applicant: KYUSHU UNIVERSITY, NATIONAL UNIVERSITY CORPORATION
    Inventors: Eiji KAWANISHI, Akio OJIDA, Motohiro NISHIDA, Yuri KATO
  • Patent number: 11754610
    Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: September 12, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Jun Ogi, Yuri Kato, Naohiko Kimizuka, Yoshihisa Matoba, Kan Shimizu
  • Publication number: 20230213475
    Abstract: The present disclosure relates to a semiconductor device and a cell potential measuring device capable of improving measurement accuracy of a potential of a solution.A semiconductor device includes a read electrode that reads a potential of a solution, a differential amplifier, a first capacitor connected in series in a loop feeding back an output of the differential amplifier to a second input different from a first input from the read electrode, a resistance element connected in parallel with the first capacitor, and a second capacitor connected between a reference electrode indicating a reference potential and the second input. The present disclosure can be applied to, for example, a cell potential measuring device.
    Type: Application
    Filed: May 27, 2021
    Publication date: July 6, 2023
    Inventors: YURI KATO, KOJI OGAWA
  • Patent number: 11606071
    Abstract: To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: March 14, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yuri Kato
  • Patent number: 11492722
    Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: November 8, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Sato, Machiko Kametani, Jun Ogi, Yuri Kato
  • Patent number: 10866211
    Abstract: The present disclosure relates to a semiconductor device and a cell potential measuring apparatus capable of amplifying and reading a potential of solution with high accuracy. A reading electrode reads the potential of the solution. A differential amplifier includes a current mirror circuit. The reading electrode is connected to a first input terminal of the differential amplifier which is connected to a gate of a first input transistor connected to a diode-connected pMOS transistor of the current mirror circuit. An output terminal of the differential amplifier is connected to a second input terminal of the differential amplifier, which is connected to a gate of a second input transistor connected to a pMOS transistor of the current mirror circuit which is not diode-connected, via a capacitor. For example, the present disclosure is applied to the cell potential measuring apparatus and the like.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 15, 2020
    Assignee: SONY CORPORATION
    Inventors: Yuri Kato, Yusuke Oike
  • Patent number: 10852292
    Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown in an electrode formation process when an electrode and an amplifier are provided on a same substrate. A diode is provided of which a cathode is connected to a previous stage of an amplifying transistor for amplifying a signal read by a read electrode for reading a potential having contact with liquid in which a specimen is input and an anode is grounded. With such a configuration, by bypassing a negative charge generated between the electrode and the amplifying transistor in the electrode formation process from the diode and discharging the negative charge toward ground so as to prevent electrostatic breakdown. This is applicable to a bioelectric potential measuring apparatus.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: December 1, 2020
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Sato, Machiko Kametani, Jun Ogi, Yuri Kato
  • Publication number: 20200331349
    Abstract: The present disclosure is a vehicle operation input apparatus that performs an input on a vehicle-mounted device that achieves a predetermined function at a plurality of levels. The apparatus obtains, as input content, display content displayed in the first position corresponding to a user input, in which a level setting is displayed, and determines a change amount based on the number of contact points corresponding to the user input.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 22, 2020
    Applicant: Mazda Motor Corporation
    Inventors: Takayoshi YAMASHITA, Shinobu KATO, Yuri KATO, Juntaro MATSUO, Eri FUJIMURA, Hado MOROKAWA
  • Publication number: 20200331321
    Abstract: A vehicle operation input apparatus that detects whether a vehicle is stopped, and controls a display to display a level setting display representing a setting of levels of a device installed in the vehicle in the first position on the display surface in mutually different display aspects depending on whether the vehicle is stopped.
    Type: Application
    Filed: April 15, 2020
    Publication date: October 22, 2020
    Applicant: Mazda Motor Corporation
    Inventors: Takayoshi YAMASHITA, Shinobu KATO, Yuri KATO, Juntaro MATSUO, Eri FUJIMURA, Hado MOROKAWA
  • Publication number: 20200295722
    Abstract: To provide a semiconductor device that makes it possible to reduce a cell circuit area and an increase in resolution. There is provided a semiconductor device including: a first region in which readout cells are arranged in an array form, the readout cells having one of input transistors included in a differential amplifier: and a second region in which reference cells are arranged in an array form, the reference cells having another input transistor included in the differential amplifier, the first region and the second region being separated from each other.
    Type: Application
    Filed: October 23, 2018
    Publication date: September 17, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Yuri KATO
  • Publication number: 20200271710
    Abstract: To achieve decreased noise and improved sensitivity by reducing parasitic capacitance in a charge detection sensor. The charge detection sensor includes a detection element, a detection electrode, and a contact. The detection element is provided on one surface of a semiconductor substrate and detects a charge. The detection electrode is provided on another surface different from the one surface of the semiconductor substrate. The contact penetrates the semiconductor substrate and electrically connects the detection electrode and the detection element. Since no wiring layer is formed between the detection element and the detection electrode, the parasitic capacitance is reduced.
    Type: Application
    Filed: August 14, 2018
    Publication date: August 27, 2020
    Inventors: JUN OGI, YURI KATO, NAOHIKO KIMIZUKA, YOSHIHISA MATOBA, KAN SHIMIZU
  • Publication number: 20200049688
    Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing electrostatic breakdown in an electrode formation process when an electrode and an amplifier are provided on a same substrate. A diode is provided of which a cathode is connected to a previous stage of an amplifying transistor for amplifying a signal read by a read electrode for reading a potential having contact with liquid in which a specimen is input and an anode is grounded. With such a configuration, by bypassing a negative charge generated between the electrode and the amplifying transistor in the electrode formation process from the diode and discharging the negative charge toward ground so as to prevent electrostatic breakdown. This is applicable to a bioelectric potential measuring apparatus.
    Type: Application
    Filed: November 17, 2017
    Publication date: February 13, 2020
    Inventors: MASAHIRO SATO, MACHIKO KAMETANI, JUN OGI, YURI KATO
  • Publication number: 20200048787
    Abstract: The present disclosure relates to a semiconductor apparatus and a potential measuring apparatus capable of preventing deterioration in signal characteristics due to parasitic capacitance caused by providing a configuration for realizing an electrode plating process when an electrode and an amplifier are provided on the same substrate. When a power source supplies a potential necessary for plating processing and a breaker reads a signal from liquid, and an amplifier amplifies and outputs the signal, the power source required for the plating processing is blocked with respect to the electrode. This is applicable to the potential measuring apparatus.
    Type: Application
    Filed: November 17, 2017
    Publication date: February 13, 2020
    Inventors: Masahiro SATO, Machiko KAMETANI, Jun OGI, Yuri KATO
  • Publication number: 20190293597
    Abstract: The present disclosure relates to a semiconductor device and a cell potential measuring apparatus capable of amplifying and reading a potential of solution with high accuracy. A reading electrode reads the potential of the solution. A differential amplifier includes a current mirror circuit. The reading electrode is connected to a first input terminal of the differential amplifier which is connected to a gate of a first input transistor connected to a diode-connected pMOS transistor of the current mirror circuit. An output terminal of the differential amplifier is connected to a second input terminal of the differential amplifier, which is connected to a gate of a second input transistor connected to a pMOS transistor of the current mirror circuit which is not diode-connected, via a capacitor. For example, the present disclosure is applied to the cell potential measuring apparatus and the like.
    Type: Application
    Filed: June 7, 2017
    Publication date: September 26, 2019
    Inventors: YURI KATO, YUSUKE OIKE
  • Patent number: 9681080
    Abstract: Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 13, 2017
    Assignee: Sony Corporation
    Inventors: Yuri Kato, Yusuke Oike
  • Patent number: 9596422
    Abstract: The present technology relates to a signal processing device and a method, an imaging device, and an imaging apparatus that are designed to reduce occurrences of A/D conversion errors. A signal processing device of the present technology includes: a comparing unit that compares an analog signal output from a unit pixel with a predetermined voltage; a switching unit that switches reference voltages to be supplied to the comparing unit as necessary, connects one of the reference voltages to the comparing unit, and connects another one of the reference voltages to a predetermined load capacitance, the reference voltages being of different gradation accuracies from each other; and a measuring unit that measures timing of a change in a result of the comparison performed by the comparing unit. The present technique can be applied to imaging devices and imaging apparatuses, for example.
    Type: Grant
    Filed: July 4, 2014
    Date of Patent: March 14, 2017
    Assignee: Sony Corporation
    Inventors: Yuri Kato, Yusuke Oike
  • Publication number: 20160212365
    Abstract: The present technology relates to a signal processing device and a method, an imaging device, and an imaging apparatus that are designed to reduce occurrences of A/D conversion errors. A signal processing device of the present technology includes: a comparing unit that compares an analog signal output from a unit pixel with a predetermined voltage; a switching unit that switches reference voltages to be supplied to the comparing unit as necessary, connects one of the reference voltages to the comparing unit, and connects another one of the reference voltages to a predetermined load capacitance, the reference voltages being of different gradation accuracies from each other; and a measuring unit that measures timing of a change in a result of the comparison performed by the comparing unit. The present technique can be applied to imaging devices and imaging apparatuses, for example.
    Type: Application
    Filed: July 4, 2014
    Publication date: July 21, 2016
    Inventors: Yuri KATO, Yusuke OIKE
  • Publication number: 20160100117
    Abstract: Disclosed is a digital-analog converter including a current generation section, a current source transistor bias voltage keeping section, a cascade transistor group switch section, and a conversion section. The current generation section has at least one current source transistor group including a plurality of current source transistors and generates an output current based on a value of a digital input signal. The current source transistor bias voltage keeping section has a plurality of cascade transistor groups each including cascade transistors connected in series to the current source transistors and keeps bias voltages of the current source transistors constant. The cascade transistor group switch section selects one of the plurality of cascade transistor groups. The conversion section performs current-voltage conversion of the output current supplied via the selected cascade transistor group.
    Type: Application
    Filed: October 9, 2015
    Publication date: April 7, 2016
    Inventors: Yuri Kato, Yusuke Oike