Abstract: An imaging system includes a camera unit and a control unit. A control signal transmission circuit of the control unit is configured to set a bias potential of a signal line to one of two or more different potentials at a timing that is set on the basis of a first video synchronization signal so as to output a control signal indicating an imaging condition of an image sensor to the signal line. A signal-processing circuit of the camera unit is configured to receive the control signal and determine the imaging condition from the control signal by determining the bias potential at a timing that is set on the basis of a second video synchronization signal.

Abstract: An imaging system includes a camera unit and a control unit. A control signal transmission circuit of the control unit is configured to set a bias potential of a signal line to one of two or more different potentials at a timing that is set on the basis of a first video synchronization signal so as to output a control signal indicating an imaging condition of an image sensor to the signal line. A signal-processing circuit of the camera unit is configured to receive the control signal and determine the imaging condition from the control signal by determining the bias potential at a timing that is set on the basis of a second video synchronization signal.

Abstract: An A/D converter includes a reference voltage generating circuit that generates a reference voltage of a ramp waveform in which a voltage value changes with time, a gray code generating circuit that outputs a gray code based on a same reference clock as the reference voltage generating circuit, a comparison circuit that compares the reference voltage with an input voltage, a latch circuit that holds a count value of the gray code based on an output signal of the comparison circuit, a code conversion circuit that serially converts the count value of the gray code held in the latch circuit into a binary code, and a calculation processing circuit that stores a count value of the binary code output from the code conversion circuit, and performs calculation processing based on the stored count value of the binary code and a next input count value of the binary code.

Abstract: A solid-state imaging device includes a two-dimensional pixel array in which unit pixels are arranged on a semiconductor substrate, each including a photoelectric conversion element, and a circuit element. When a plurality of adjacent unit pixels are defined as one pixel group set, a plurality of pixel group sets are arranged in the two-dimensional pixel array. In the one pixel group set, a periphery of the one pixel group set is surrounded by an insulating element isolation region that isolates elements in the semiconductor substrate, except for an intermediate portion between two adjacent unit pixels. In the one pixel group set, two adjacent photoelectric conversion elements are arranged so that two floating diffusions respectively connected to the two adjacent photoelectric conversion elements are opposed to each other with the circuit element interposed therebetween. A transistor shared by the one pixel group set is provided in the intermediate portion.

Abstract: A solid-state image pickup device is provided with a two-dimensional pixel array wherein unit pixels are arrayed on a semiconductor substrate, the unit pixels respectively including photoelectric conversion elements configured to convert inputted light into electric signals, and circuit elements configured to read out the electric signals thus converted. The unit pixels are formed in at least one shared well region surrounded by an insulating element isolation region that penetrates the semiconductor substrate from the front surface to the rear surface and isolates the elements from each other. Each shared well region is biased to a predetermined potential via well contact sections of a number that is smaller than that of the unit pixels.

Abstract: A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.

Abstract: An A/D converter includes a reference voltage generating circuit that generates a reference voltage of a ramp waveform in which a voltage value changes with time, a gray code generating circuit that outputs a gray code based on a same reference clock as the reference voltage generating circuit, a comparison circuit that compares the reference voltage with an input voltage, a latch circuit that holds a count value of the gray code based on an output signal of the comparison circuit, a code conversion circuit that serially converts the count value of the gray code held in the latch circuit into a binary code, and a calculation processing circuit that stores a count value of the binary code output from the code conversion circuit, and performs calculation processing based on the stored count value of the binary code and a next input count value of the binary code.

Abstract: A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.

Abstract: An image-capturing device includes a solid-state image-capturing device in which a first substrate and a second substrate are electrically connected through connection units. The image-capturing device includes: a pixel unit in which a plurality of pixels, each of which has a photoelectric conversion element for generating a photoelectric conversion signal according to an intensity of incident light disposed on the first substrate, are disposed in a two-dimensional matrix and configured to output a photoelectric conversion signal generated by each of the pixels as a pixel signal for every row; a plurality of signal processing units, each of which is disposed for every one or more columns of the plurality of pixels provided in the pixel unit, performs predetermined signal processing on the pixel signal output from the pixel of a corresponding column, and outputs a processed signal including a plurality of signals after the signal processing is performed.

Abstract: An image-capturing device includes a solid-state image-capturing device in which a first substrate and a second substrate are electrically connected through connection units. The image-capturing device includes: a pixel unit in which a plurality of pixels, each of which has a photoelectric conversion element for generating a photoelectric conversion signal according to an intensity of incident light disposed on the first substrate, are disposed in a two-dimensional matrix and configured to output a photoelectric conversion signal generated by each of the pixels as a pixel signal for every row; a plurality of signal processing units, each of which is disposed for every one or more columns of the plurality of pixels provided in the pixel unit, performs predetermined signal processing on the pixel signal output from the pixel of a corresponding column, and outputs a processed signal including a plurality of signals after the signal processing is performed.

Abstract: An imaging device includes a pixel unit including a plurality of pixels, the pixels being arranged in a two-dimensional matrix form, m digital signal output circuits, each of which is arranged for a column of the pixel unit or for every two or more columns, and outputs an n-bit digital signal corresponding to a level of a pixel signal of a pixel of the corresponding column, m latch circuits, each of which is arranged to correspond to the digital signal output circuit, and includes n latch units that hold respective bit signals of the digital signal of the corresponding digital signal output circuit, respectively, and (m?1) switches, each of which is arranged to correspond to the latch unit, and transfers the digital signal held in the corresponding latch unit to the corresponding latch unit in the neighboring latch circuit.

Abstract: A signal transfer circuit may include first to nth switches that are respectively connected to bits of an n-bit digital signal output from a digital signal generating circuit and controlled by a transfer control circuit, a first memory circuit including first to nth memories that respectively hold bits of the n-bit digital signal input through the first to nth switches and are serially connected to each other, a second memory circuit including (n+1)th to mth memories that hold a digital signal and are serially connected to each other, an output signal of the nth memory of the first memory circuit being input to the (n+1)th memory of a first stage, and (n+1)th to mth switches that are connected to output signals of the (n+1)th to mth memories of the second memory circuit and controlled by a read control circuit.

Abstract: An imaging device includes a pixel unit including a plurality of pixels, the pixels being arranged in a two-dimensional matrix form, m digital signal output circuits, each of which is arranged for a column of the pixel unit or for every two or more columns, and outputs an n-bit digital signal corresponding to a level of a pixel signal of a pixel of the corresponding column, m latch circuits, each of which is arranged to correspond to the digital signal output circuit, and includes n latch units that hold respective bit signals of the digital signal of the corresponding digital signal output circuit, respectively, and (m-1) switches, each of which is arranged to correspond to the latch unit, and transfers the digital signal held in the corresponding latch unit to the corresponding latch unit in the neighboring latch circuit.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.

Abstract: An analog-to-digital converter may include an annular delay circuit that includes a plurality of delay units connected in an annular shape, each of the plurality of delay units delaying a pulse current that is input to each of the plurality of delay units, a current source that outputs an electric current, in accordance with an input analog signal, to selected delay units, which is selected from among the plurality of delay units, and a digital signal generation unit that generates a digital signal in accordance with a number of circulations per predetermined period of time of the pulse current circulating around the annular delay circuit.