Abstract: A parking control device includes a detector and a determiner. The detector receives, from an ultrasonic sensor which transmits an ultrasonic wave and receives a reflected wave corresponding to the ultrasonic wave, a signal based on the reflected wave. The detector further detects a detection point group being an aggregate of a plurality of detection points of two parked vehicle groups adjacent to a parking space between the two parked vehicle groups, based on the signal. The determiner determines whether the parking space is an end-on parking space or a parallel parking space based on a position of at least a depression shape in at least a contour pattern being a pattern of the detection point group.

Abstract: A parking control device includes a controller and a notification unit. The controller executes a parking assistance control for making a vehicle travel from a drop-off position of an occupant of the vehicle to a parking space that is preliminarily determined and making the vehicle be parked in the parking space by automated driving. The controller ceases the parking assistance control in a case where an obstacle is present on a traveling route of the vehicle including the parking space. The notification unit provides a notification that the parking assistance control is stopped. The notification unit transmits information indicating that the parking assistance control is ceased to a device having identification information preliminarily associated with identification information of the vehicle.

Abstract: A parking control device includes a detector and a determiner. The detector receives, from an ultrasonic sensor which transmits an ultrasonic wave and receives a reflected wave corresponding to the ultrasonic wave, a signal based on the reflected wave. The detector further detects a detection point group being an aggregate of a plurality of detection points of two parked vehicle groups adjacent to a parking space between the two parked vehicle groups, based on the signal. The determiner determines whether the parking space is an end-on parking space or a parallel parking space based on a position of at least a depression shape in at least a contour pattern being a pattern of the detection point group.

Abstract: A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulator 209 incorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section 11, a complex arithmetic section 101, a coefficient determination section 51, and raised COS filters 41 and 42. Spreading code multiplication section 11 multiplies transmit data DPDCH1 by a spreading code Cd1. Complex arithmetic section 101 performs complex arithmetic on an output signal output from spreading code multiplication section 11 and a scrambling code Sn, and performs conversion to complex data. Coefficient determination section 51 determines a filter coefficient Ad1n based on a gain factor ?d1 that determines transmission power. Raised COS filters 41 and 42 band-limit the complex data using the filter coefficient.

Abstract: A delta-sigma modulator and A/D converter capable of doubling an oversampling ratio without increasing an operating speed of the circuit at an A/D modulator provided with a delta-sigma modulator which carries out differentiation and integration processing on two channels of analog input. A delta-sigma modulator is configured with a first sampling section that samples a first analog input, a second sampling section that samples a second analog input, a third sampling section that samples an output of a quantizer corresponding to the first analog input, a fourth sampling section that samples the output of the quantizer corresponding to the second analog input, and a switch control circuit that controls analog switches so as to carry out time division processing on integration of the output of the first sampling section and the output of the third sampling section and integration of the output of the second sampling section and the output of the fourth sampling section.

Abstract: A delta-sigma modulator and A/D converter is capable of doubling an oversampling ratio without increasing the operating speed of the circuit at an A/D modulator provided with a delta-sigma modulator which carries out differentiation and integration processing on two channels of analog input. Delta-sigma modulator 100 is configured with first sampling section 110 that samples first analog input, second sampling section 120 that samples second analog input, third sampling section 130 that samples output of quantizer 180 corresponding to the first analog input, fourth sampling section 140 that samples output of quantizer 180 corresponding to the second analog input, and switch control circuit 200 that controls analog switches so as to carry out time division processing on integration of the output of first sampling section 110 and the output of third sampling section 130 and integration of the output of second sampling section 120 and the output of fourth sampling section 140.

Abstract: While a switch SW4 is connected to “a”-terminal side, offset of a differential output voltage “A?” of a D/A converter 500a (500b) is held in a comparator 400, and is reflected to a reference voltage. Thereafter, the switch SW4 is switched to a “b”-terminal side, and offset of a differential output voltage “A+” of the D/A converter 500a (500b) is measured by the comparator 400. An error signal is outputted to a counter 412 so as to count up the counter 412. Such an operation is repeatedly carried out in which the count value is added to 1.7 V and then the added count value is inputted into the D/A converter 500a (500b), and such a count value latched in a latch at timing when the error signal is inverted is defined as an offset correction value.

Abstract: A modulator, and more particularly an HPSK modulator, is disclosed that enables the circuit scale to be reduced and also enables power consumption to be reduced. An HPSK modulator 209 incorporated in a radio communication apparatus or the like is equipped with a spreading code multiplication section 11, a complex arithmetic section 101, a coefficient determination section 51, and raised COS filters 41 and 42. Spreading code multiplication section 11 multiplies transmit data DPDCH1 by a spreading code Cd1. Complex arithmetic section 101 performs complex arithmetic on an output signal output from spreading code multiplication section 11 and a scrambling code Sn, and performs conversion to complex data. Coefficient determination section 51 determines a filter coefficient Ad1n based on a gain factor ?d1 that determines transmission power. Raised COS filters 41 and 42 band-limit the complex data using the filter coefficient.

Abstract: While a switch SW4 is connected to “a”-terminal side, offset of a differential output voltage “A−” of a D/A converter 500a (500b) is held in a comparator 400, and is reflected to a reference voltage. Thereafter, the switch SW4 is switched to a “b”-terminal side, and offset of a differential output voltage “A+” of the D/A converter 500a (500b) is measured by the comparator 400. An error signal is outputted to a counter 412 so as to count up the counter 412. Such an operation is repeatedly carried out in which the count value is added to 1.7 V and then the added count value is inputted into the D/A converter 500a (500b), and such a count value latched in a latch at timing when the error signal is inverted is defined as an offset correction value.