Patents by Inventor Yusuke Ikeda
Yusuke Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11641025Abstract: A method for manufacturing an all-solid-state battery includes a battery unit producing step, a flattening step, and a stacking step. In the battery unit producing step, a battery unit having a plate shape is produced through a pressing step in which a laminate including at least one each of a positive electrode active material layer, a solid electrolyte layer, and a negative electrode active material layer is pressed in a thickness direction of the laminate with a first pressure. In the flattening step, the battery unit is flattened by pressing the produced battery unit in the thickness direction with a second pressure equal to or lower than the first pressure while heating the battery unit to a temperature equal to or higher than a temperature at which the battery unit softens and is deformed. In the stacking step, a plurality of the flattened battery units are stacked.Type: GrantFiled: January 14, 2021Date of Patent: May 2, 2023Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Yusuke Ikeda, Masato Ono
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Patent number: 11632513Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: GrantFiled: October 21, 2021Date of Patent: April 18, 2023Assignee: Sony Semiconductor Solutions CorporationInventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Publication number: 20230104085Abstract: The range-finding apparatus (1) includes a light source (200), an optical receiver (1103), a setting unit (100), a detector (1100), and a calculation unit (300). The light source (200) projects light with a first irradiation pattern in a first period and projects light with a second irradiation pattern in a second period. The optical receiver (1103) receives light to output a pixel signal. The setting unit (100) sets a reference signal on the basis of the pixel signal in the first period. The detector (1100) detects whether or not the pixel signal varies from the reference signal by a first value or more in the second period and outputs a first detection signal indicative of a result obtained by the detection. The calculation unit (300) calculates a distance to a to-be-measured object using the first detection signal.Type: ApplicationFiled: January 22, 2021Publication date: April 6, 2023Inventors: TAKAHIRO AKAHANE, SHUN KAIZU, YUSUKE IKEDA, YASUTAKA KIMURA, SHINICHIROU ETOU, TAKESHI OYAKAWA, NAOTO NAGAKI, EIJI HIRATA, HIROSHI YUASA
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Publication number: 20230074464Abstract: The range-finding apparatus (1) includes an optical receiver (110), a light source unit (200), a converter (134), and a calculation unit (300). The optical receiver (110) receives light to output a pixel signal. The light source unit (200) projects light with a first irradiation pattern in a first period and projects light with a second irradiation pattern in a second period. The converter (134) sequentially converts the pixel signal bit by bit using binary search to output a first digital signal and a second digital signal, the first digital signal being output by performing the conversion with a first bit width in the first period, the second digital signal being output by performing the conversion with a second bit width in the second period, the second bit width being less than the first bit width. The calculation unit (300) calculates a distance on the basis of the first digital signal and the second digital signal.Type: ApplicationFiled: January 25, 2021Publication date: March 9, 2023Inventors: TAKAHIRO AKAHANE, YUSUKE IKEDA, SHUN KAIZU, EIJI HIRATA, HIROSHI YUASA, SHINICHIROU ETOU, YASUTAKA KIMURA, TAKESHI OYAKAWA, NAOKI YOSHIMOCHI
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Publication number: 20230011014Abstract: Solid-state imaging devices are disclosed. In one example, a solid-state imaging device includes a conversion circuit connected to a vertical signal line of a pixel array, a voltage generation circuit that outputs a predetermined voltage, and a reference voltage generation circuit that receives the predetermined voltage and outputs a reference voltage. The reference voltage generation circuit includes an operational amplifier that amplifies the predetermined voltage and outputs the reference voltage, a capacitive element having one end connected to an input of the operational amplifier that is different from an input that receives the predetermined voltage, a first switching circuit that connects the other end of the capacitive element to either the predetermined voltage output from the voltage generation circuit or a feedback loop of the operational amplifier, and a second switching circuit that selectively connects the one end of the capacitive element to the feedback loop of the operational amplifier.Type: ApplicationFiled: November 18, 2020Publication date: January 12, 2023Inventors: Shinichirou Etou, Yusuke Ikeda
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Patent number: 11515563Abstract: A stacking apparatus provided with a flexible conveyor plate (20), a clamp mechanism (25) for holding a sheet-shaped member carried on the conveyor plate (20) against the conveyor plate (20), and an adjustment mechanism able to adjust the degree of curvature of the conveyor plate (20). When stacking a new sheet-shaped member (1) carried on the conveyor plate (20) onto already stacked sheet-shaped members (1), the adjustment mechanism makes the conveyor plate (20) deform from a flat state to a curved state to make the new sheet-shaped member (1) carried on the conveyor plate (20) deform from a flat state to a curved state.Type: GrantFiled: December 14, 2020Date of Patent: November 29, 2022Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Masato Ono, Yuichi Itoh, Yusuke Ikeda, Kazuhito Kato
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Publication number: 20220355189Abstract: The value of a first parameter is updated while a touch operation on a touch screen is continued. A first game control is executed when a first touch operation is received from a user and then a second touch operation is received after a touch operation of updating the value of the first parameter to a first value is released.Type: ApplicationFiled: August 6, 2020Publication date: November 10, 2022Inventor: Yusuke Ikeda
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Publication number: 20220285684Abstract: A negative electrode material for a lithium ion secondary battery includes particles in a state in which a plurality of flat graphite particles are aggregated or bonded, and in the negative electrode material, with respect to a volume-based particle diameter measured by a laser diffraction/scattering method, a cumulative value at 9.516 ?m is 8.0% or less, a standard deviation of a particle size distribution is 0.22 or less, and a specific surface area is 3.0 m2/g or less.Type: ApplicationFiled: July 31, 2019Publication date: September 8, 2022Inventors: Takayuki MIYAUCHI, Takeshi SATO, Yusuke IKEDA, Takuya KAGAWA
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Patent number: 11418750Abstract: An imaging element according to a first aspect includes: a successive approximation resistor type analog-digital converter that converts an analog signal output from a pixel including a photoelectric conversion part into a digital signal, in which the successive approximation resistor type analog-digital converter has a preamplifier having a band limiting function. An imaging element according to a second aspect includes a DAC in which the successive approximation resistor type analog-digital converter uses a capacitance element to convert a digital value after AD conversion to an analog value, and sets the analog value to a comparison reference for comparison with an analog input voltage.Type: GrantFiled: April 3, 2019Date of Patent: August 16, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Shinichirou Etou, Yusuke Ikeda
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Patent number: 11405571Abstract: Changing the analog gain for each of columns while suppressing an expansion of area and an increase in power consumption. A solid-state imaging apparatus (1, 1A) according to an embodiment includes: converters (10A to 10D) connected to a vertical signal line (VSL) extending from a pixel array unit (30); a voltage generator (20) that is connected to a plurality of voltage lines and outputs reference voltages having mutually different voltage values individually to the plurality of voltage lines; wiring lines (L10 to L31, L20 to L23) connecting the converter and the plurality of voltage lines; and switches (SW0 to SW3) provided on the wiring line and configured to perform changeover of the voltage lines connected to the converter to one of the plurality of voltage lines.Type: GrantFiled: July 25, 2019Date of Patent: August 2, 2022Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventor: Yusuke Ikeda
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Publication number: 20220201232Abstract: A photodetection device according to the present disclosure includes: a first pixel that is configured to generate a first pixel signal; a reference signal generator that is configured to generate a reference signal; and a first comparator including a first power supply circuit and a first comparison circuit, the first power supply circuit configured to generate a first power supply voltage on the basis of a power supply voltage supplied from a first power supply node and a bias voltage and configured to output the first power supply voltage from an output terminal, and the first comparison circuit configured to operate on the basis of the first power supply voltage and configured to perform a comparison operation on the basis of the first pixel signal and the reference signal.Type: ApplicationFiled: March 6, 2020Publication date: June 23, 2022Inventors: Youhei Oosako, Yusuke Ikeda, Yosuke Ueno, Masahiro Segami
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Publication number: 20220184504Abstract: A game program for getting a computer to execute such a routine that playing characters battle each other in a three dimensional virtual space so as to obtain battle points, the obtained battle points are collected as total values, and the total values are ranked, the playing character belonging to one of two or more groups, each group being divided into two or more teams . The game program for getting the computer to execute a routine of dividing the playing characters into specific teams within the group, a routine of storing data showing to which team the playing character belongs; a routine of battling between the teams of the different groups; a routine of totalizing and storing the battle points obtained by the respective playing characters in the battle for every team; a routine of totalizing the battle point every group for all teams and storing the results, respectively giving a ranking; and a routine of outputting the ranking.Type: ApplicationFiled: December 9, 2021Publication date: June 16, 2022Applicant: SQUARE ENIX CO., LTD.Inventors: Tomohiro HASEGAWA, Yusuke IKEDA
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Patent number: 11350056Abstract: An image sensor including a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed, and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal. The comparator includes differential pair transistors, a first load transistor connected in series with a first transistor of the differential pair, and a second load transistor connected in series with a second transistor of the differential pair. The first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input, the second transistor of the differential pair accepts a predetermined voltage as a gate input.Type: GrantFiled: January 11, 2019Date of Patent: May 31, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Katzutoshi Tomita, Yusuke Ikeda, Sachio Akebono, Takashi Moue
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Publication number: 20220094871Abstract: An image sensor including a pixel array section in which a plurality of pixels including photoelectric conversion units is disposed, and a comparator that compares an analog pixel signal output from the pixels to a predetermined reference signal, and outputs a comparison result according to a signal level of the pixel signal. The comparator includes differential pair transistors, a first load transistor connected in series with a first transistor of the differential pair, and a second load transistor connected in series with a second transistor of the differential pair. The first transistor of the differential pair accepts a signal obtained by combining the pixel signal and the predetermined reference signal as a gate input, the second transistor of the differential pair accepts a predetermined voltage as a gate input.Type: ApplicationFiled: January 11, 2019Publication date: March 24, 2022Inventors: Katzutoshi Tomita, Yusuke Ikeda, Sachio Akebono, Takashi Moue
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Patent number: 11283460Abstract: An A/D converter and electronic equipment are disclosed. In one example, an A/D converter includes a comparator circuit and a first transistor. The comparator circuit compares a threshold voltage (Vth) to a pixel signal (SVSL). The first transistor has a control terminal and forms a clamp circuit, and receives an input of a result of the comparison. When the clamp circuit is turned on (closed), the first transistor equalizes currents flowing to a first predetermined position and a second predetermined position or equalizes voltages at the first predetermined position and the second predetermined position, the first predetermined position and the second predetermined position being connected to each other at the time of clamping. This makes it possible to suppress occurrence of streaking in a case where an excessive input is applied to a pixel signal line side.Type: GrantFiled: October 2, 2019Date of Patent: March 22, 2022Assignee: Sony Semiconductor Solutions CorporationInventors: Yasufumi Hino, Yusuke Ikeda, Shinichirou Etou, Kazutoshi Tomita
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Publication number: 20220046199Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: ApplicationFiled: October 21, 2021Publication date: February 10, 2022Inventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Patent number: 11178350Abstract: It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines. The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.Type: GrantFiled: July 10, 2018Date of Patent: November 16, 2021Assignee: Sony Semiconductor Solutions CorporationInventors: Yosuke Ueno, Golan Zeituni, Noam Eshel, Yusuke Ikeda, Kiyoshi Makigawa
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Publication number: 20210297623Abstract: Changing the analog gain for each of columns while suppressing an expansion of area and an increase in power consumption. A solid-state imaging apparatus (1, 1A) according to an embodiment includes: converters (10A to 10D) connected to a vertical signal line (VSL) extending from a pixel array unit (30); a voltage generator (20) that is connected to a plurality of voltage lines and outputs reference voltages having mutually different voltage values individually to the plurality of voltage lines; wiring lines (L10 to L31, L20 to L23) connecting the converter and the plurality of voltage lines; and switches (SW0 to SW3) provided on the wiring line and configured to perform changeover of the voltage lines connected to the converter to one of the plurality of voltage lines.Type: ApplicationFiled: July 25, 2019Publication date: September 23, 2021Inventor: YUSUKE IKEDA
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Publication number: 20210280897Abstract: A method for manufacturing an all-solid-state battery includes a battery unit producing step, a flattening step, and a stacking step. In the battery unit producing step, a battery unit having a plate shape is produced through a pressing step in which a laminate including at least one each of a positive electrode active material layer, a solid electrolyte layer, and a negative electrode active material layer is pressed in a thickness direction of the laminate with a first pressure. In the flattening step, the battery unit is flattened by pressing the produced battery unit in the thickness direction with a second pressure equal to or lower than the first pressure while heating the battery unit to a temperature equal to or higher than a temperature at which the battery unit softens and is deformed. In the stacking step, a plurality of the flattened battery units are stacked.Type: ApplicationFiled: January 14, 2021Publication date: September 9, 2021Inventors: Yusuke IKEDA, Masato ONO
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Publication number: 20210257653Abstract: A stacking apparatus provided with a flexible conveyor plate (20), a clamp mechanism (25) for holding a sheet-shaped member carried on the conveyor plate (20) against the conveyor plate (20), and an adjustment mechanism able to adjust the degree of curvature of the conveyor plate (20). When stacking a new sheet-shaped member (1) carried on the conveyor plate (20) onto already stacked sheet-shaped members (1), the adjustment mechanism makes the conveyor plate (20) deform from a flat state to a curved state to make the new sheet-shaped member (1) carried on the conveyor plate (20) deform from a flat state to a curved state.Type: ApplicationFiled: December 14, 2020Publication date: August 19, 2021Inventors: Masato ONO, Yuichi ITOH, Yusuke IKEDA, Kazuhito KATO