Patents by Inventor Yusuke Tokieda

Yusuke Tokieda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6230291
    Abstract: This invention discloses a microcomputer and a method of its burn-in test in which the burn-in test for detecting the initial defects of the parts necessary to detect the defects of the microcomputer is carried out while keeping the microcomputer mounted on the same burn-in test device. When a burn-in test mode signal is activated by a mode decoder, a mode switching circuit carries out switching so as to activate either one of a ROM dump mode signal or a test ROM execution signal, by means of a mode switching signal from a mode switching terminal. A central processing unit dumps data of the user ROM when the ROM dump mode signal is activated, and executes a program stored in the test ROM when the test ROM execution signal is activated, to gain access to various parts of the microcomputer. A reset signal is used as the mode switching signal.
    Type: Grant
    Filed: August 28, 1998
    Date of Patent: May 8, 2001
    Assignee: NEC Corporation
    Inventor: Yusuke Tokieda
  • Patent number: 5771361
    Abstract: In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external access request if it contains an instruction to access an external memory which is connected to an external terminal. A bus controller is responsive to the request for producing a data timing signal and one of read and write signals. An external address bus and an external data bus are connected to the bus controller. An internal address bus is connected to the CPU for transporting an internal address signal.
    Type: Grant
    Filed: June 14, 1995
    Date of Patent: June 23, 1998
    Assignee: NEC Corporation
    Inventors: Yusuke Tokieda, Hiroshi Katsuta
  • Patent number: 5511013
    Abstract: A microcomputer includes a plurality of peripheral circuits accessed by a central processing unit for a reading/writing of the peripheral circuits. Each of the external terminals supplies a selection signal indicative of use or non-use of a corresponding peripheral circuit. Each selection signal is supplied to a gate circuit provided for the corresponding peripheral circuit, for controlling permission and inhibition of application of a clock signal or a strobe signal to the corresponding peripheral circuit. Thus, neither the clock nor the strobe signal is supplied to the peripheral circuits which are not used in an actual application system, with the result that a low power consumption, highly reliable microcomputer is realized.
    Type: Grant
    Filed: July 12, 1994
    Date of Patent: April 23, 1996
    Assignee: NEC Corporation
    Inventors: Yusuke Tokieda, Hiroshi Katsuta