Abstract: An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

Abstract: The invention addresses providing a technology that enables it to restrain a temperature rise because of current consumed by a quantum semiconductor and wiring conductors for control. A quantum calculator disclosed herein comprises a first refrigeration tube to cool a metal body; a refrigerator framing which encloses inside the metallic body and the first refrigeration tube; a quantum bit array chip having a plurality of silicon-spin quantum bits; and multiple control wiring conductors to drive the quantum bit array chip. The quantum bit array chip is placed on the metal body and made up of multiple regions and sub-regions, each of the regions performing a quantum operation independently. The multiple control wiring conductors are connected to the multiple regions and sub-regions respectively as multiple groups of control wiring conductors. The multiple control wring conductors are disposed across the first refrigeration tube.

Abstract: An equalizer that has a wide variable gain range and that can implement equalization for a communication medium such as on-board wiring or a cable having various wiring lengths. The equalizer includes a core circuit and a source follower connected to a subsequent stage of the core circuit. The core circuit includes a differential pair including a first transistor and a second transistor, and a zero point generation circuit connected between a second terminal of the first transistor and a second terminal of the second transistor. The source follower includes a third transistor and a fourth transistor, a variable bias current source is connected to the third and fourth transistors, and a load in which a capacitive element and a resistor element are connected in series via a switching element is connected to wiring that connects the third and fourth transistors to an output terminal.

Abstract: A wireless receiver and a wireless reception method provide: to determine a gain based on a first resistor having a first temperature characteristic and a second resistor having a second temperature characteristic different from the first resistance; to output an output of the first resistor and an output of the second resistor, or a ratio between the output of the first resistor and the output of the second resistor; and to switches the gain of the first circuit based on the outputs or the ratio between the outputs.

Abstract: The equalizer has a first differential pair having a first transistor and a second transistor and a second differential pair having a third transistor and a fourth transistor. A first terminal of the first transistor and a first terminal of the third transistor are connected to each other, and a first terminal of the second transistor and a first terminal of the fourth transistor are connected to each other, so that the first differential pair and the second differential pair have common input terminals. Also, resistors are respectively connected to second terminals of the first, second, third, and fourth transistors, a first zero point generation circuit is connected between the second terminal of the first transistor and the second terminal of the second transistor, and a second zero point generation circuit is connected between the second terminal of the third transistor and the second terminal of the fourth transistor.

Abstract: A wireless receiver and a wireless reception method provide: to determine a gain based on a first resistor having a first temperature characteristic and a second resistor having a second temperature characteristic different from the first resistance; to output an output of the first resistor and an output of the second resistor, or a ratio between the output of the first resistor and the output of the second resistor; and to switches the gain of the first circuit based on the outputs or the ratio between the outputs.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: Provided is an amplifier with a test oscillator for a high frequency characteristic monitor, which has small power loss in a normal operation state and secures good noise performance while it is possible to equip both a transmitter IC and a receiver IC with the amplifier. In a high frequency IC including an amplifier including an inductive load and a test oscillator arranged in a same chip, the test oscillator commonly uses the inductive load of the amplifier, the amplifier has a bias voltage terminal to switch an operation state into an active state/inactive state, and the oscillator has a bias voltage terminal to switch an operation state into an active state/inactive state. In a test operation mode, the amplifier is inactivated and the test oscillator is activated and in a normal operation mode, the amplifier is activated and the test oscillator is inactivated.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: A clock data recovery circuit which has a high degree of jitter tolerance and can alleviate increase in the phase number of a multi-phase clock, power consumption, and a semiconductor chip area is provided. Each circuit of plural edge detection circuits comprises a first edge detection circuit and a second edge detection circuit. The first detection circuit detects that a data edge leads in phase more than ?1 phase from an edge detection phase, the second detection circuit detects that the data edge laggs in phase more than +1 phase from the edge detection phase. In response to the first output signal or the second output signal, the edge detection phase is changed by the amount of ?1 phase or +1 phase. When the data edge is detected in the range of ±1 phase, a next edge detection phase is maintained in the current state.

Abstract: The present invention provides an oscillator and a communication system using the oscillator, in particular, an LC oscillator adapted to lessen phase noise deterioration due to harmonic distortions and increase the amplitude of oscillation, thereby having a favorable low phase noise characteristic. The oscillator comprises at least one voltage to current converter consisting of a transistor and a resonator comprising two LC tanks consisting of a pair of conductive elements and inductive elements. A feedback loop is formed such that an output terminal of the voltage to current converter is connected to the resonator and a current input to the resonator is converted to a voltage which is in turn fed back to an input terminal of the voltage to current converter. Inductive elements constituting the two LC tanks constituting the resonator are mutually inductively couple and a coefficient of the mutual induction is about ?0.6.

Abstract: In a high frequency antenna switch module, an I/O interface generates various control signals for controlling a switch module on the basis of a system data signal and a system clock, a decoder generates a switch control signal SWCNT for controlling a switch in response to a control signal CNT in the control signals, a timing detector for switch-ports switching generates a switch-port switching detection signal t_sw in response to the switch control signal, a frequency control signal generator generates frequency control signals ICONT and CCONT in response to the signal t_sw, and a negative voltage generation circuit generates a negative voltage output signal NVG_OUT while switching the frequency of the clock signal generated in the negative voltage generation circuit to different frequencies in response to signals ICONT and CCONT. The switch switches the paths among the plural switch ports in response to the signals SWCNT and NVG_OUT.

Abstract: A transfer impedance from input terminals of a resonator to output terminals of the resonator is larger than a driving-point impedance of the input terminals of the resonator at an oscillation frequency. The input terminals of the resonator are connected with the drain terminals of transistors Q1 and Q2 that are outputs of a differential amplifier, and the output terminals of the resonator are connected with gate terminals of the transistors Q1 and Q2 that are inputs of the differential amplifier. With this configuration, during the oscillating operation, the oscillation voltage amplitude of the gate terminals of the transistors Q1 and Q2 becomes larger than the oscillation voltage amplitude of the drain terminals. Therefore, it is possible to prevent the transistor, which is oscillating, from operating in a triode region, and suppress the deterioration of the Q-factor.

Abstract: The present invention provides an oscillator and a communication system using the oscillator, in particular, an LC oscillator adapted to lessen phase noise deterioration due to harmonic distortions and increase the amplitude of oscillation, thereby having a favorable low phase noise characteristic. The oscillator comprises at least one voltage to current converter consisting of a transistor and a resonator comprising two LC tanks consisting of a pair of conductive elements and inductive elements. A feedback loop is formed such that an output terminal of the voltage to current converter is connected to the resonator and a current input to the resonator is converted to a voltage which is in turn fed back to an input terminal of the voltage to current converter. Inductive elements constituting the two LC tanks constituting the resonator are mutually inductively couple and a coefficient of the mutual induction is about ?0.6.

Abstract: A transfer impedance from input terminals of a resonator to output terminals of the resonator is larger than a driving-point impedance of the input terminals of the resonator at an oscillation frequency. The input terminals of the resonator are connected with the drain terminals of transistors Q1 and Q2 that are outputs of a differential amplifier, and the output terminals of the resonator are connected with gate terminals of the transistors Q1 and Q2 that are inputs of the differential amplifier. With this configuration, during the oscillating operation, the oscillation voltage amplitude of the gate terminals of the transistors Q1 and Q2 becomes larger than the oscillation voltage amplitude of the drain terminals. Therefore, it is possible to prevent the transistor, which is oscillating, from operating in a triode region, and suppress the deterioration of the Q-factor.