Patents by Inventor Yuta Tezen

Yuta Tezen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7560725
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.
    Type: Grant
    Filed: September 15, 2005
    Date of Patent: July 14, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu
  • Patent number: 7491984
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
    Type: Grant
    Filed: November 2, 2004
    Date of Patent: February 17, 2009
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
  • Patent number: 7462867
    Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 ?m and a depth of 10 ?m were formed at 10 ?m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 ?m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.
    Type: Grant
    Filed: September 12, 2005
    Date of Patent: December 9, 2008
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yuta Tezen
  • Patent number: 7141444
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.
    Type: Grant
    Filed: March 12, 2001
    Date of Patent: November 28, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Hiroshi Yamashita, Seiji Nagai, Toshio Hiramatsu
  • Patent number: 7052979
    Abstract: When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: May 30, 2006
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Shiro Yamazaki, Yuta Tezen, Toshio Hiramatsu
  • Publication number: 20060060866
    Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 ?m and a depth of 10 ?m were formed at 10 ?m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 ?m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.
    Type: Application
    Filed: September 12, 2005
    Publication date: March 23, 2006
    Applicant: Toyoda Gosel Co., Ltd.
    Inventor: Yuta Tezen
  • Publication number: 20060027831
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.
    Type: Application
    Filed: September 15, 2005
    Publication date: February 9, 2006
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Kioke, Yuta Tezen, Toshio Hiramatsu
  • Patent number: 6979584
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: December 27, 2005
    Assignee: Toyoda Gosei Co, Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu
  • Patent number: 6967122
    Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 ?m and a depth of 10 ?m were formed at 10 ?m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 ?m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: November 22, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Yuta Tezen
  • Publication number: 20050093099
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, stripe, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer 31 can be prevented.
    Type: Application
    Filed: November 2, 2004
    Publication date: May 5, 2005
    Applicant: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
  • Patent number: 6861305
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations. A GaN layer 31 is subjected to etching, so as to form an island-like structure having a shape of, for example, dot, strip, or grid, thereby providing a trench/mesa structure, and a mask 4 is formed at the bottom of the trench such that the upper surface of the mask 4 is positioned below the top surface of the GaN layer 31. A GaN layer 32 is lateral-epitaxially grown with the top surface 31a of the mesa and sidewalls 31b of the trench serving as nuclei, to thereby bury the trench, and then epitaxial growth is effected in the vertical direction. In the upper region of the GaN layer 32 formed above the mask 4 through lateral epitaxial growth, propagation of threading dislocations contained in the GaN layer is 31 can be prevented.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: March 1, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai
  • Patent number: 6855620
    Abstract: A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: February 15, 2005
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Seiji Nagai, Yuta Tezen
  • Patent number: 6830948
    Abstract: By using a mask 4, a first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, striped-shaped, or grid-like structure, so as to provide a trench/post. Thus, without removing the mask 4 formed on a top surface of the upper layer of the post, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, with a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. The second Group III nitride compound layer 32 does not grow epitaxially on the mask 4. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth and a region having less threading dislocations can be formed in the buried portion of the trench.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 14, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Akira Kojima, Toshio Hiramatsu, Yuta Tezen
  • Publication number: 20040123796
    Abstract: When a substrate layer (desired semiconductor crystal) made of a group III nitride compound is grown on a base substrate comprising a lot of projection parts, a cavity in which a semiconductor crystal is not deposited may be formed between each projection part although it depends on conditions such as the size of each projection part, arranging interval between each projection part and crystal growth. So when the thickness of the substrate layer is sufficiently larger compared with the height of the projection part, inner stress or outer stress become easier to act intensively to the projection part. As a result, such stress especially functions as shearing stress toward the projection part. When the shearing stress becomes larger, the projection part is ruptured. So utilizing the shearing stress enables to separate the base substrate and the substrate layer easily.
    Type: Application
    Filed: October 9, 2003
    Publication date: July 1, 2004
    Inventors: Seiji Nagai, Kazuyoshi Tomita, Shiro Yamazaki, Yuta Tezen, Toshio Hiramatsu
  • Publication number: 20040048448
    Abstract: A GaN layer 31 is subjected to etching, so as to form an island-like structure having, for example, a dot, stripe, or grid shape, thereby providing a trench/mesa structure including mesas and trenches whose bottoms sink into the surface of a substrate base 1. Subsequently, a GaN layer 32 is lateral-epitaxially grown with the top surfaces of the mesas and sidewalls of the trenches serving as nuclei, to thereby fill upper portions of the trenches (depressions of the substrate base 1), and then epitaxial growth is effected in the vertical direction. In this case, propagation of threading dislocations contained in the GaN layer 31 can be prevented in the upper portion of the GaN layer 32 that is formed through lateral epitaxial growth.
    Type: Application
    Filed: August 5, 2003
    Publication date: March 11, 2004
    Inventors: Masayoshi Koike, Seiji Nagai, Yuta Tezen
  • Patent number: 6680957
    Abstract: A semiconductor laser 101 comprises a sapphire substrate 1, an AlN buffer layer 2, Si-doped GaN n-layer 3, Si-doped Al0.1Ga0.9N n-cladding layer 4, Si-doped GaN n-guide layer 5, an active layer 6 having multiple quantum well (MQW) structure in which about 35 Å in thickness of GaN barrier layer 62 and about 35 Å in thickness of Ga0.95In0.05N well layer 61 are laminated alternately, Mg-doped GaN p-guide layer 7, Mg-doped Al0.1Ga0.9N p-cladding layer 8, and Mg-doped GaN p-contact layer 9 are formed successively thereon. A ridged hole injection part B which contacts to a ridged resonator part A is formed to have the same width as the width w of an Ni electrode 10. Holes transmitted from the Ni electrode 10 are injected to the active layer 6 with high current density, and electric current threshold for laser oscillation can be decreased. Electric current threshold can be improved more effectively by forming also the p-guide layer 7 to have the same width as the width w of the Ni electrode 10.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: January 20, 2004
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Masayoshi Koike, Shiro Yamasaki, Yuta Tezen, Seiji Nagai, Akira Kojima, Toshio Hiramatsu
  • Patent number: 6631149
    Abstract: A guide layer is formed to have a superlattice structure comprising five pairs of layers of AlGaN and InN, each having a thickness of about 10 nm. The guide layer has a total thickness of about 0.1 &mgr;m. The guide layer so structured has a reduced elastic constant such that the guide layer acts as a stress relieving layer.
    Type: Grant
    Filed: October 16, 2000
    Date of Patent: October 7, 2003
    Assignees: Toyoda Gosei Co., Ltd., Japan Science and Technology Corporation
    Inventors: Yuta Tezen, Masayoshi Koike
  • Publication number: 20030162340
    Abstract: A sapphire substrate 1 is etched so that each trench has a width of 10 &mgr;m and a depth of 10 &mgr;m were formed at 10 &mgr;m of intervals in a stripe pattern. Next, an AlN buffer layer 2 having a thickness of approximately 40 nm is formed mainly on the upper surface and the bottom surface of the trenches of the substrate 1. Then a GaN layer 3 is formed through vertical and lateral epitaxial growth. At this time, lateral epitaxial growth of the buffer layer 21, which was mainly formed on the upper surface of the trenches, filled the trenches and thus establishing a flat top surface. The portions of the GaN layer 3 formed above the top surfaces of the mesas having a depth of 10 &mgr;m exhibited significant suppression of threading dislocation in contrast to the portions formed above the bottoms of the trenches.
    Type: Application
    Filed: March 18, 2003
    Publication date: August 28, 2003
    Inventor: Yuta Tezen
  • Publication number: 20030134446
    Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/mesa such that layer different from the first Group III nitride compound semiconductor layer 31 is exposed at the bottom portion of the trench. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, laterally, with a top surface of the mesa and a sidewall/sidewalls of the trench serving as a nucleus, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. Etching may be performed until a cavity portion is provided in the substrate.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 17, 2003
    Inventors: Masayoshi Koike, Yuta Tezen, Hiroshi Yamashita, Seiji Nagai, Toshio Hiramatsu
  • Publication number: 20030119239
    Abstract: The present invention provides a Group III nitride compound semiconductor with suppressed generation of threading dislocations.
    Type: Application
    Filed: September 30, 2002
    Publication date: June 26, 2003
    Inventors: Masayoshi Koike, Yuta Tezen, Toshio Hiramatsu, Seiji Nagai