Patents by Inventor Yutaka Doi

Yutaka Doi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10156044
    Abstract: An intersecting track includes: two main tracks; a pair of first guide portions disposed in the main tracks and guide a pair of first guide wheels of the vehicle; a pair of crossover tracks disposed over the main tracks to intersect each other; a second guide portion disposed inside each of the pair of crossover tracks and guides a second guide wheel; a switching portion that switches a direction of the vehicle to a direction along the main tracks and a direction along the crossover track; and a switching device disposed in an intersecting area of the second guide portions in the pair of crossover tracks, selectively switches a direction to a direction along one of the second guide portions and a direction along the other of the second guide portions, and guides the second guide wheel in any one of the directions.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: December 18, 2018
    Assignee: MITSUBISHI HEAVY INDUSTRIES ENGINEERING, LTD.
    Inventors: Kosaku Murase, Eisuke Okano, Yutaka Doi
  • Publication number: 20170183827
    Abstract: An intersecting track includes: two main tracks; a pair of first guide portions disposed in the main tracks and guide a pair of first guide wheels of the vehicle; a pair of crossover tracks disposed over the main tracks to intersect each other; a second guide portion disposed inside each of the pair of crossover tracks and guides a second guide wheel; a switching portion that switches a direction of the vehicle to a direction along the main tracks and a direction along the crossover track; and a switching device disposed in an intersecting area of the second guide portions in the pair of crossover tracks, selectively switches a direction to a direction along one of the second guide portions and a direction along the other of the second guide portions, and guides the second guide wheel in any one of the directions.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 29, 2017
    Inventors: Kosaku MURASE, Eisuke OKANO, Yutaka DOI
  • Publication number: 20040091208
    Abstract: Waveguides comprising dielectric mirrors and dielectric cladding preferably formed by modifying a portion of a dielectric layer to adjust its index of refraction relative to other portions of the dielectric layer.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 13, 2004
    Inventor: Yutaka Doi
  • Patent number: 6727711
    Abstract: Methods and devices for testing connectivity between connectors on a circuit board include utilizing a bias board having a photoconductive layer coated with a light-transmissive electrically conductive layer in conjunction with a light source and a voltage source to alternately charge and discharge conductors. A conductor discharged by connecting it to a ground via the bias board is determined to be electrically connected to a previously charged conductor if current flows between the conductor and the ground.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: April 27, 2004
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Publication number: 20040070479
    Abstract: A solenoid having a plurality of stacked gapped circle windings, with each winding being rotated relative to any adjacent windings, and with each winding lying in a plane perpendicular to a common axis.
    Type: Application
    Filed: October 10, 2002
    Publication date: April 15, 2004
    Inventors: Yutaka Doi, Bruce Lee
  • Publication number: 20040012978
    Abstract: Waveguides formed via direct deposition of reflective material on isolated surfaces of the waveguides rather than on every surface of the waveguides are described. It is contemplated that direct deposition facilitates deposition on isolated surfaces. Deposition only on isolated surfaces reduces costs and risks. Cost is reduced by reducing the amount of reflective material required. Risk of metal particles plugging the waveguide reduced both by the decrease in amount of reflective material used, and in the method of depositing it.
    Type: Application
    Filed: July 18, 2002
    Publication date: January 22, 2004
    Inventor: Yutaka Doi
  • Publication number: 20030146482
    Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a solid, substantially planar optical wave-guide laminated onto the substrate layer. The printed wiring board further comprises at least one of a laminating material or a cladding material coupled to the wave-guide, and at least one additional layer coupled to the laminating material or the cladding material.
    Type: Application
    Filed: December 19, 2002
    Publication date: August 7, 2003
    Inventor: Yutaka Doi
  • Publication number: 20030138335
    Abstract: A tube pump comprising a tube formed beforehand into a shape adapted for the inner circumferential face of the housing. With this configuration, the tube can be used without problems even when the inner circumferential face of the housing is small and when the curvature of the inner circumferential face is large, and squeezing can be carried out by applying a small pressure force to the tube. Hence, the size of the pump is prevented from being made larger, and breakage of the tube owing to repeated deformations does not occur because the amount of deformation of the tube is reduced. Furthermore, synthetic resins having high chemical resistance can be used as materials of the tube. Hence, unlike a rubber tube, the tube of the present invention is suited for a wide range of applications.
    Type: Application
    Filed: December 20, 2002
    Publication date: July 24, 2003
    Inventors: Yutaka Doi, Fumio Nakamura, Katsuhiko Morita, Nagao Tamagawa
  • Patent number: 6590398
    Abstract: Methods and devices for testing connectivity between connectors on a circuit board include utilizing a bias board having a photoconductive layer coated with a light-transmissive electrically conductive layer in conjunction with a light source and a voltage source to alternately charge and discharge conductors. A conductor discharged by connecting it to a ground via the bias board is determined to be electrically connected to a previously charged conductor if current flows between the conductor and the ground.
    Type: Grant
    Filed: July 6, 2000
    Date of Patent: July 8, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Publication number: 20030112616
    Abstract: Compositions and methods are provided whereby electronic layered components or stacks may be produced that comprise a) a substrate layer; b) an electronic component; and c) an electromagnetic interference shielding component, wherein the component comprises a first insulating layer, an electrically conductive layer, and a second insulating layer.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventor: Yutaka Doi
  • Publication number: 20030115008
    Abstract: A calibrated vector network analyzer (VNA) test system comprising two variable pitch test heads coupled to a VNA.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 19, 2003
    Inventor: Yutaka Doi
  • Patent number: 6559656
    Abstract: Measurement of the permittivity of thin films is facilitated through the use of a short cylindrical metal cavity containing parallel plates between which a specimen to be measured is placed. The use of such parallel plates contained within such a cavity is particularly advantageous when swept frequency measurement methods utilizing frequency ranges from 0 to 20 GHz are employed. A test fixture which is preferred for use in providing such a cavity is disclosed as are methods of using the test fixture.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: May 6, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Patent number: 6539157
    Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a hollow, mirror-clad optical wave-guide laminated onto the substrate layer. The printed wiring board further comprises a cover material coupled to the wave-guide.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: March 25, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventor: Yutaka Doi
  • Patent number: 6510392
    Abstract: Methods and apparatus for improved impedance measurements are which allow for shorter delays during recalibration and which eliminate the need to physically disconnect and reconnect test leads after initial calibration has been completed. In particular, an adjustment factor is calculated based on impedances measured during initial calibration and is used to adjust future impedance measurements. Moreover, a plurality of loads having pre-measured impedances are switchably connected to the meter such that re-calibration using said loads may be accomplished without the physical connection or disconnection of test leads. The plurality of loads are preferably incorporated into a test board which also comprises additional test leads and a switching mechanism to alternately connect the various loads and test leads to the meter.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: January 21, 2003
    Assignee: Honeywell Advanced Circuits, Inc.
    Inventors: Yutaka Doi, Stephen L. Tisdale
  • Publication number: 20020167330
    Abstract: Methods and devices for testing connectivity between connectors on a circuit board include utilizing a bias board having a photoconductive layer coated with a light-transmissive electrically conductive layer in conjunction with a light source and a voltage source to alternately charge and discharge conductors. A conductor discharged by connecting it to a ground via the bias board is determined to be electrically connected to a previously charged conductor if current flows between the conductor and the ground.
    Type: Application
    Filed: June 25, 2002
    Publication date: November 14, 2002
    Inventor: Yutaka Doi
  • Publication number: 20020135991
    Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a solid, substantially planar optical waveguide laminated onto the substrate layer. The printed wiring board further comprises at least one of a laminating material or a cladding material coupled to the wave-guide, and at least one additional layer coupled to the laminating material or the cladding material.
    Type: Application
    Filed: December 28, 2000
    Publication date: September 26, 2002
    Inventor: Yutaka Doi
  • Publication number: 20020118026
    Abstract: Measurement of the permittivity of thin films is facilitated through the use of a short cylindrical metal cavity containing parallel plates between which a specimen to be measured is placed. The use of such parallel plates contained within such a cavity is particularly advantageous when swept frequency measurement methods utilizing frequency ranges from 0 to 20 GHz are employed. A test fixture which is preferred for use in providing such a cavity is disclosed as are methods of using the test fixture.
    Type: Application
    Filed: December 28, 2000
    Publication date: August 29, 2002
    Inventor: Yutaka Doi
  • Publication number: 20020085823
    Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a hollow, mirror-clad optical wave-guide laminated onto the substrate layer. The printed wiring board further comprises a cover material coupled to the wave-guide.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventor: Yutaka Doi
  • Publication number: 20020087277
    Abstract: Methods and apparatus for improved impedance measurements are which allow for shorter delays during recalibration and which eliminate the need to physically disconnect and reconnect test leads after initial calibration has been completed. In particular, an adjustment factor is calculated based on impedances measured during initial calibration and is used to adjust future impedance measurements. Moreover, a plurality of loads having pre-measured impedances are switchably connected to the meter such that re-calibration using said loads may be accomplished without the physical connection or disconnection of test leads. The plurality of loads are preferably incorporated into a test board which also comprises additional test leads and a switching mechanism to alternately connect the various loads and test leads to the meter.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventors: Yutaka Doi, Stephen L. Tisdale
  • Publication number: 20020085360
    Abstract: Compositions and methods are provided whereby electronic components may be produced that comprise a) a substrate layer; b) an insulator layer coupled to the substrate layer, wherein the insulator layer comprises at least two different kinds of embedded passive components; and c) at least one additional layer coupled to the insulator layer. A preferred method comprises a) imaging an insulator layer to create a first pattern on the insulator layer; b) etching the first pattern on the insulator layer to create a first compartment in the insulator layer; c) filling the first compartment with a first material to form a first passive component; d) imaging the insulator layer to create a second pattern on the insulator layer; e) etching the second pattern on the insulator layer to create a second compartment in the insulator layer; and f) filling the second compartment with a second material to form a second passive component.
    Type: Application
    Filed: December 28, 2000
    Publication date: July 4, 2002
    Inventor: Yutaka Doi