Patents by Inventor Yutaka Ikeda

Yutaka Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7280860
    Abstract: Noninvasive living body measuring apparatuses are described, a representative one of which includes: (a) a light source unit for irradiating a measurement region of a living body; (b) a light-receiving unit for detecting optical information from an irradiated measurement region; (c) a first holding unit for holding the light source unit and the light-receiving unit; (d) a second holding unit for holding the first holding unit so as to be movable; and (e) a mounting unit for mounting the second holding unit onto a living body.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: October 9, 2007
    Assignee: Sysmex Corporation
    Inventors: Yutaka Ikeda, Takeo Saitou, Rokusaburo Kimura, Toshiyuki Ozawa
  • Publication number: 20070164709
    Abstract: A battery pack includes a first switching element which shuts off a discharging current flowing to a battery cell and a second switching element which shuts off a charging current. A positive temperature coefficient thermistor is inserted between a gate control terminal of a protective control circuit and a gate of at least one of the switching elements, and a resistor is connected between the gate and a source of the switching element. The positive temperature coefficient thermistor is thermally connected to one or more of the first and second switching elements and/or to the battery cell. Thus, an abnormally overheated state of one or more of the switching elements or the battery cell leads to an increase in the resistance of the positive temperature coefficient thermistor causing shut-off of the switching elementthereby protecting the battery pack.
    Type: Application
    Filed: December 18, 2006
    Publication date: July 19, 2007
    Inventors: Shuji TSUBAKI, Kazuto MIYAGAWA, Yutaka IKEDA
  • Publication number: 20070082712
    Abstract: A mobile phone apparatus is provided which can register the settings for a ringing operation when receiving a telephone call depending on the situation.
    Type: Application
    Filed: March 31, 2005
    Publication date: April 12, 2007
    Applicant: Matsushita Electric Industrial Co., LTD.
    Inventors: Yutaka Ikeda, Emi Satou
  • Publication number: 20070072301
    Abstract: A system for checking measurement results is provided with a urine qualitative analyzer for measuring the specific gravity of a urine, urinary particle analyzer for measuring urine conductivity, and a computer. The urine specific gravity measured by the urine qualitative analyzer, and the urine conductivity measured by the urinary particle analyzer are respectively transmitted to the computer. The correlative relationship between urine specific gravity and urine conductivity is stored in the memory of the computer, and the computer determines whether or not the received urine specific gravity and conductivity match the correlative relationship, and this determination result is output.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventors: Masakazu Fukuda, Yutaka Ikeda, Hiromi Onomichi
  • Publication number: 20060289478
    Abstract: In a method for sorting PTC elements having different resistance-temperature characteristics, a predetermined voltage that allows a current to sufficiently decay is applied to each of PTC elements A and B, and the PTC elements are sorted on the basis of the difference between the times required for the currents passing through the PTC elements B to reach a predetermined value (e.g., 52 mA).
    Type: Application
    Filed: August 24, 2006
    Publication date: December 28, 2006
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshitaka NAGAO, Hiroshi IBARAGI, Yutaka IKEDA, Kazuto MIYAGAWA, Yoshiaki ABE
  • Publication number: 20060274872
    Abstract: A sampling section (102) is provided for generating a sampling signal (103) by sampling an input signal (101) using a sampling clock (106) which is faster than a data speed of the input signal (101). A waveform shaping section (104) is provided for I) processing (e.g. inverting a pulse) the sampling signal (103), so as to shape a restored digital signal obtained from a pulse of the input signal (101), and II) outputting the restored digital signal as an output signal (105). In this way, it becomes possible to provide: A) a waveform shaping method and a waveform shaping device, each of which is capable of correcting distortion in an input signal by means of a simple method or configuration; B) a waveform shaping program that realizes the waveform shaping method or the waveform shaping device; and C) a recording medium storing therein the waveform shaping program.
    Type: Application
    Filed: March 19, 2004
    Publication date: December 7, 2006
    Inventors: Yutaka Ikeda, Takashi Aramaki
  • Patent number: 7016612
    Abstract: A digital optical communication device includes an optical reception circuit converting an optical signal received from any external source to an electric signal, a decoding circuit decoding the electric signal resultant from conversion by the optical reception circuit and judging whether or not the decoding is normally completed, a reception light intensity level judgement circuit judging an intensity level of received light based on the electric signal, a coding circuit coding transmission data, and an optical transmission circuit determining a light emission intensity based on result of the judgement by the reception light intensity level judgement circuit and on result of the judgement by the decoding circuit, and converting the transmission data coded by the coding circuit to an optical signal with the light emission intensity.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: March 21, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Ikeda, Takashi Nishimura
  • Patent number: 7005827
    Abstract: A starting circuit for a single-phase induction motor includes a motor starting positive characteristic thermistor and a triac arranged in a series connection, and a triac control positive characteristic thermistor connected in parallel with the motor starting positive characteristic thermistor, and including one terminal thereof connected to a gate of the triac. The triac control positive characteristic thermistor has a volume in the range of about 4.5 mm3 to about 30 mm3. The relationship of (?2×V×sin 45°)/R?I is maintained with the triac control positive characteristic thermistor within an operating temperature range, where V represents a root-mean-square value of a power source voltage, R represents a resistance of the triac control positive characteristic thermistor, and I represents a gate turn-on current of the triac. The gate turn-on current I at an operating temperature of about 25° C. is about 20 mA or less.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: February 28, 2006
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yutaka Ikeda, Hiroki Tanaka, Toshiharu Hirota
  • Publication number: 20060017418
    Abstract: A starting circuit for a single-phase induction motor includes a motor starting positive characteristic thermistor and a triac arranged in a series connection, and a triac control positive characteristic thermistor connected in parallel with the motor starting positive characteristic thermistor, and including one terminal thereof connected to a gate of the triac. The triac control positive characteristic thermistor has a volume in the range of about 4.5 mm3 to about 30 mm3. The relationship of (?2×V×sin 45°)/R?I is maintained with the triac control positive characteristic thermistor within an operating temperature range, where V represents a root-mean-square value of a power source voltage, R represents a resistance of the triac control positive characteristic thermistor, and I represents a gate turn-on current of the triac. The gate turn-on current I at an operating temperature of about 25° C. is about 20 mA or less.
    Type: Application
    Filed: July 7, 2005
    Publication date: January 26, 2006
    Inventors: Yutaka Ikeda, Hiroki Tanaka, Toshiharu Hirota
  • Publication number: 20050277838
    Abstract: Noninvasive biometric body measuring devicees are described, a representative one of which includes: an obtaining part obtaining biometric information from the measured region of a living body; a pressing part for pressing the living body close to the measured region; a pressure sensor detecting a press force of the pressing part; a control part controlling the press force of the pressing part based on a detected value of the pressure sensor; and an analyzing part analyzing the biometric information obtained by the obtaining part in such a state that the living body is pressed by the pressing part.
    Type: Application
    Filed: June 10, 2005
    Publication date: December 15, 2005
    Inventors: Yutaka Ikeda, Toshiyuki Ozawa, Takeo Saitou
  • Patent number: 6963477
    Abstract: A semiconductor switching element performs operations of bringing a current path from a power supply to a load into conduction and interrupting the path and is controlled by an operating-mode control circuit so as to operate in a first operating mode in which a conductive operation is shifted to an interrupt operation by using a change in resistance of a first positive-temperature-coefficient thermistor when the temperature of a temperature detection portion increases and reaches a predetermined interrupt temperature, and to be in a second operating mode in which the interrupt operation is shifted to the conductive operation by using a change in resistance of a second positive-temperature-coefficient thermistor when the temperature of the temperature detection portion decreases and reaches a return temperature, which is lower than the interrupt temperature by a predetermined value.
    Type: Grant
    Filed: August 12, 2003
    Date of Patent: November 8, 2005
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Yutaka Ikeda
  • Publication number: 20040184591
    Abstract: A communication apparatus of the present invention has a first storing unit for storing information detected by a caller information detector, a caller identifying unit for identifying a calling place of a caller based on the information stored in the first storing unit, a second storing unit for storing information of the calling place identified by the caller identifying unit, a third storing unit for storing predetermined information, and a controller for controlling a display unit to display combined information of the calling place information stored in the second storing unit and the predetermined information stored in the third storing unit. The communication apparatus has a controller for extracting voice data selected by a voice data selecting unit and controlling the voice converting unit to output a voice signal, when the plurality of voice data correspond to the caller information detected by the caller information detector.
    Type: Application
    Filed: May 10, 2004
    Publication date: September 23, 2004
    Inventors: Hiroki Shimomura, Katsuyuki Kajiwara, Sadaka Mitsuo, Michiaki Tanaka, Yuji Hirai, Yoshihiro Ishimura, Yutaka Ikeda
  • Publication number: 20040162471
    Abstract: Noninvasive living body measuring apparatuses are described, a representative one of which includes: (a) a light source unit for irradiating a measurement region of a living body; (b) a light-receiving unit for detecting optical information from an irradiated measurement region; (c) a first holding unit for holding the light source unit and the light-receiving unit; (d) a second holding unit for holding the first holding unit so as to be movable; and (e) a mounting unit for mounting the second holding unit onto a living body.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 19, 2004
    Applicant: Sysmex Corporation
    Inventors: Yutaka Ikeda, Takeo Saitou, Rokusaburo Kimura, Toshiyuki Ozawa
  • Publication number: 20040042142
    Abstract: A semiconductor switching element performs operations of bringing a current path from a power supply to a load into conduction and interrupting the path and is controlled by an operating-mode control circuit so as to operate in a first operating mode in which a conductive operation is shifted to an interrupt operation by using a change in resistance of a first positive-temperature-coefficient thermistor when the temperature of a temperature detection portion increases and reaches a predetermined interrupt temperature, and to be in a second operating mode in which the interrupt operation is shifted to the conductive operation by using a change in resistance of a second positive-temperature-coefficient thermistor when the temperature of the temperature detection portion decreases and reaches a return temperature, which is lower than the interrupt temperature by a predetermined value.
    Type: Application
    Filed: August 12, 2003
    Publication date: March 4, 2004
    Applicant: Murata Manufacturing Co., Ltd.
    Inventor: Yutaka Ikeda
  • Patent number: 6654300
    Abstract: A semiconductor memory device includes an internal voltage generation circuit controlling an internal voltage supplied to an internal circuit in accordance with a reference voltage, a reference voltage generation circuit generating the reference voltage, a plurality of signal terminals for transmitting and receiving a signal to and from an outside of the semiconductor memory device, and a reference voltage change indication circuit for indicating a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit during a test.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: November 25, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yutaka Ikeda
  • Patent number: 6643217
    Abstract: In a test mode, read data is output from a memory array with each of N latch circuits in an output circuit being set to an operating state under the control of a latency setting circuit. Thus, the data transmission period can be set shorter in the test mode than in a normal data reading operation, and a time required for testing the read data in the test mode is shortened.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: November 4, 2003
    Assignee: Mitsubshi Denki Kabushiki Kaisha
    Inventor: Yutaka Ikeda
  • Patent number: 6634006
    Abstract: A packet data communication device has a lower-layer communication tool including at least a first lower-layer portion without an error-detection and retransmission function, and an upper-layer communication tool having both an IrTran-P function and an error-detection and retransmission function. When the first lower-layer portion is used, the upper-layer communication tool performs error-detection and retransmission of arbitrary-length packet data.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: October 14, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Ikeda, Shuichiro Ono
  • Publication number: 20030165077
    Abstract: In a test mode, read data is output from a memory array with each of N latch circuits in an output circuit being set to an operating state under the control of a latency setting circuit. Thus, the data transmission period can be set shorter in the test mode than in a normal data reading operation, and a time required for testing the read data in the test mode is shortened.
    Type: Application
    Filed: August 26, 2002
    Publication date: September 4, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yutaka Ikeda
  • Publication number: 20030151961
    Abstract: A semiconductor memory device includes an internal voltage generation circuit controlling an internal voltage supplied to an internal circuit in accordance with a reference voltage, a reference voltage generation circuit generating the reference voltage, a plurality of signal terminals for transmitting and receiving a signal to and from an outside of the semiconductor memory device, and a reference voltage change indication circuit for indicating a change of the reference voltage on the basis of a binary input signal to each of the signal terminals with respect to the reference voltage generation circuit during a test.
    Type: Application
    Filed: August 13, 2002
    Publication date: August 14, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Yutaka Ikeda
  • Patent number: 6480439
    Abstract: Consuming current must be reduced in each operation state of a semiconductor device which operates in synchronized with an external clock signal. However, in each operation state, for satisfying the stability of an operation and a speedup, the suppression of consuming current has been performed under difficult circumstances. For solving this problem, a clock generation circuit generating an internal clock signal based on an external clock signal is activated during a specific time period when a clock synchronization circuit is in a state of inactivation.
    Type: Grant
    Filed: April 10, 2001
    Date of Patent: November 12, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroto Tokutome, Yutaka Ikeda