Abstract: A power-down determination circuit calculates the horizontal frequency and vertical frequency, respectively, employing a clock signal obtained from a multiplier circuit and horizontal synchronization signal and vertical synchronization signal obtained from a TMDS decode circuit. The power-down determination circuit then determines whether an input digital signal does or does not have a decodable video format by comparing the calculated horizontal frequency and vertical frequency with horizontal frequencies and vertical frequencies stored beforehand, for output of a power-down control signal indicative of the determination. Thus, in the case where the input digital signal does not have a decodable format, the power-down control signal controls a video/audio processing circuit to enter a power-down mode.

Abstract: A ringing detector detects mosquito noise and ringing for outputting an image signal smoothed by a horizontal/vertical high-pass filter when mosquito noise and ringing are detected while outputting the image signal as such when neither mosquito noise nor ringing is detected, thereby properly correcting the image signal without reducing the texture specific to the image signal also in a portion continuously exhibiting fine details.

Abstract: On a display (100) end, maker codes and device codes are read from all STBs (110˜112) connected to the display (100) to create a connected-device table. When a user presses a button on a remote controller, the display receives a remote control code outputted from the remote controller, searches the connected-device table for a maker code and a device code that match the maker code and the device code included in the remote control code, controls a selector (105) so that a reception interface that is connected to an STB whose maker code and device code match those included in the remote control code is connected to a display section (102), thereby to display AV data transmitted from the STB on the display section (102).

Abstract: A vertical HPF and a horizontal HPF receive a video signal 101, and extract only a high frequency component in the vertical/horizontal directions, respectively. Absolute value taking parts take an absolute value of the high frequency components, respectively, and change their values to positive values. A horizontal accumulating/adding part and a vertical accumulating/adding part accumulate/add an input signal so as to output a vertical one-dimensional signal and a horizontal one-dimensional signal, respectively, each periodically having a peak value in the respective vertical and horizontal directions. A horizontal peak detecting part detects a horizontal peak position according to the horizontal one-dimensional signal. A vertical peak detecting part detects a vertical peak position according to the vertical one-dimensional signal and identifies a format thereof.

Abstract: In a baseband video transmission system (BTS1) for transmission of a video signal (SV) at a baseband based on the DVI standard, a transmitting device (100) multiplexes a data signal (SD) representing data other than video during at least one blanking period of component video signals (SB, SG, SR) of the video signal (SV) to generate a DVI signal (Sdvi). A receiving device (104) receives the DVI signal (Sdvi), and extracts the data signal (SD) from the received DVI signal (Sdvi).

Abstract: In a signal transmission apparatus and a signal reception apparatus according to the present invention, the signal transmission apparatus side comprises a time-base compression unit (101) for compressing an audio signal on the time axis to output a time-base-compressed audio signal, and a multiplexing unit (102) for multiplexing a video signal, a control signal, and the time-base-compressed audio signal to output a multiplexed video-audio-control signal to the outside.

Abstract: A video signal processing circuit synthesizes a video signal and a graphic signal on the basis of a display switching control signal, inverts a synthesized signal on the time axis for each of a forward scanning period and a backward scanning period, and output a display signal. A speed modulating signal control circuit inverts the binarized display switching control signal on the time axis for each of the forward scanning period and the backward scanning period, expands the pulse width thereof, and feeds the display switching control signal to a speed modulating signal generating circuit. The speed modulating signal generating circuit subjects a display signal to first-order differentiation, inverts the polarity of a differentiated signal in the backward scanning signal, sets a portion, corresponding to the graphic signal, in the differentiated signal on the basis of the display switching control signal at a zero level, and generates a speed modulating signal.

Abstract: A signal transmission system according to the present invention comprises: a signal transmission unit (101) that includes a MPEG decoder (101) which receives digital broadcasting and outputs a luminance signal Y and two color difference signals PB/PR, and a transmission path encoding circuit (103) which encodes the YPBPR outputted from the MPEGU decoder (102) into signals in the forms suited to a transmission path and transmits the encoded signals; and a signal reception unit (104) that includes a transmission path decoding circuit (105) which receives the encoded YPBPR and decodes them, a Y processing circuit (106) which processes the decoded luminance signal Y, a chrominance processing circuit (107) which processes the respective decoded color difference signals PB/PR, a signal conversion circuit (108) which converts the YPBPR outputted from the Y processing circuit (106) and the chrominance processing circuit (107) into RGB signals, and a display device (108) which displays the RGB signals.

Abstract: A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor 4, input synchronizing signal processor 8, programmable signal processor 6 and output synchronizing pulse processor 9. A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory 5 enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.

Abstract: A video signal of an interlaced scanning system having 525 scanning lines and a vertical scanning frequency of 60 Hz is converted to a video signal having 1050 scanning lines and a vertical scanning frequency of 120 Hz, for displaying an image by bidirectional scanning. A vertical synchronizing signal is subjected to offset processing by a ¼ horizontal scanning period when an odd field is started, thereby keeping interlaced relation between odd and even fields. The vertical synchronizing signal is subjected to offset processing by a ½ horizontal scanning period every frame, so that the scanning direction for each scanning line is reversed every frame.

Abstract: An object is to provide a vertical contour correcting device for a video signal which reduces noise without deteriorating effect of the entire contour correction. A vertical contour correcting device (VCP1) which corrects vertical contour components (S1v, S1v′) of a video signal (S1) with a given quantity of correction (K) to enhance the vertical contour (Ev) of the video signal (S1) comprises a vertical contour component extracting device (3) for detecting said vertical contour components (S1v, S1v′) from said video signal (S1), a vertical contour component correlation detector (3, 29, 8c, 8d, 4) for detecting correlation between horizontally adjacent vertical contour components (Sb, Sb′, Sb′′) from said detected vertical contour components (S1v, S1v′), and a controller (5) for determining said quantity of correction (K) on the basis of said detected correlation (Sj1), thereby varying the quantity of correction (K) in accordance with the correlation (Sj1).

Abstract: A video signal processing apparatus which can process video signals with different formats simply by switching between programs for processing video signals. Different system clock signals are sent to the input and output processes by employing a programmable signal processor 4, input synchronizing signal processor 8, programmable signal processor 6 and output synchronizing pulse processor 9. A method for processing the video signal can be flexibly changed simply by switching between signal processing programs for programmable signal processors. In addition, the use of a memory 5 enables the signal, which is processed using the system clock signal in the input process, to be processed using the system clock signal in the output process. The present invention thus allows the processing of video signals with many different signal formats. The design of efficient circuitry will greatly reduce costs and production processes.

Abstract: A broadcasting reception apparatus includes a display unit for presenting a display showing a plurality of channels, with which the user can recognize whether decoding software programs for decoding program signals being currently broadcast via each channel are held in a library buffer, or not, thereby making possible pleasant zapping.

Abstract: A video signal processing device comprising an operating element array for processing video signals according to commands given from the outside, memories for temporarily storing the video signals according to commands given from the outside, and a network 3 for connecting the operating element array and the storage units according to commands given from the outside, thereby making it possible to switch ways of processing digitized video signals according to commands from the outside.

Abstract: A video signal converter converts a first video signal into a second video signal by changing the number of scanning lines. A horizontal pulse synchronized with the first video signal is fed into a PLL circuit, which generates a first clock signal synchronized with the horizontal pulse. The first video signal undergoes A/D conversion by sampling with the first clock signal. The converter receives a first digital video signal which has undergone the A/D conversion, the first clock signal, the horizontal pulse, and a vertical pulse synchronized with the first video signal, and thus changes a number of scanning lines of the first video signal. The converter, next, writes a second digital video signal into a memory by synchronizing the first clock signal.

Abstract: A television receiver comprising an information extracting circuit for extracting information from a format or content of an input video signal, a video signal processing circuit for processing this video signal by a program or data, a memory for storing the program and data, a CPU for controlling, operating or driving these elements, and a display device for displaying an image. The video signal processing circuit can, under the control of the CPU, decode the signal, correct or set the picture quality such as gradation and sharpness, or adaptively process an on-screen display based on the input video signal. The television receiver is also able to adaptively extend the functions of the television receiver corresponding to various signal formats.

Abstract: A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center cart of a picture can be horizontally compressed A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position or the picture can also be changed.

Abstract: A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.

Abstract: A video signal compression apparatus extracts a specific value written in a read only memory at every system clock pulse. The specific value can be varied at every clock pulse. Therefore, for example, only the center part of a picture can be horizontally compressed. A FIFO memory may be used. It is possible to select a mode with a fixed compression ratio or a mode in which a compression ratio varies at every clock pulse. Further, the fixed compression ratio can be set from the outside. Display position of the picture can also be changed.

Abstract: A video signal is reproduced by adjusting the amplitude of a horizontal high frequency signal, a vertical high frequency signal and a vertical temporal high frequency signal. Helper signals can be demodulated even if the helper signal levels vary due to receiving conditions. The number of circuits can be reduced by using a common circuit for amplitude adjustment of the helper signal and for automatic color control of a chrominance signal.