Patents by Inventor Yutaka Sugawara

Yutaka Sugawara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Remote processing and memory utilization
    Patent number: 9037669
    Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: May 19, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
    Publication number: 20140237045
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Application
    Filed: August 26, 2013
    Publication date: August 21, 2014
    Applicant: International Business Machines Coroporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • T-STAR INTERCONNECTION NETWORK TOPOLOGY
    Publication number: 20140044006
    Abstract: According to one embodiment of the present invention, a system for network communication includes an M dimensional grid of node groups, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one and each node comprises a router and intra-group links directly connecting each node in each node group to every other node in the node group. In addition, the system includes inter-group links directly connecting each node in each node group to a node in each neighboring node group in the M dimensional grid.
    Type: Application
    Filed: August 8, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara
  • T-STAR INTERCONNECTION NETWORK TOPOLOGY
    Publication number: 20140044015
    Abstract: According to one embodiment of the present invention, a method of constructing network communication for a grid of node groups is provided, the grid including an M dimensional grid, each node group including N nodes, wherein M is greater than or equal to one and N is greater than one, wherein each node includes a router. The method includes directly connecting each node in each node group to every other node in the node group via intra-group links and directly connecting each node in each node group of the M dimensional grid to a node in each neighboring node group in the M dimensional grid via inter-group links.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Philip Heidelberger, Robert M. Senger, Yutaka Sugawara
  • REMOTE PROCESSING AND MEMORY UTILIZATION
    Publication number: 20140047060
    Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
    Type: Application
    Filed: August 9, 2012
    Publication date: February 13, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Reproducibility in a multiprocessor system
    Patent number: 8595554
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • REMOTE PROCESSING AND MEMORY UTILIZATION
    Publication number: 20130290473
    Abstract: According to one embodiment of the present invention, a system for operating memory includes a first node coupled to a second node by a network, the system configured to perform a method including receiving the remote transaction message from the second node in a processing element in the first node via the network, wherein the remote transaction message bypasses a main processor in the first node as it is transmitted to the processing element. In addition, the method includes accessing, by the processing element, data from a location in a memory in the first node based on the remote transaction message, and performing, by the processing element, computations based on the data and the remote transaction message.
    Type: Application
    Filed: August 13, 2012
    Publication date: October 31, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Noel A. Eisley, Philip Heidelberger, James A. Kahle, Fabrizio Petrini, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Low delay and area efficient soft error correction in arbitration logic
    Patent number: 8533567
    Abstract: There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.
    Type: Grant
    Filed: August 9, 2010
    Date of Patent: September 10, 2013
    Assignee: International Business Machines Corporation
    Inventor: Yutaka Sugawara
  • Embedding global barrier and collective in torus network with each node combining input from receivers according to class map for output to senders
    Patent number: 8521990
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: August 27, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidelberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • Distributed parallel messaging for multiprocessor systems
    Patent number: 8458267
    Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Philip Heidelberger, Valentina Salapura, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • LOW DELAY AND AREA EFFICIENT SOFT ERROR CORRECTION IN ARBITRATION LOGIC
    Publication number: 20120036412
    Abstract: There is provided an arbitration logic device for controlling an access to a shared resource. The arbitration logic device comprises at least one storage element, a winner selection logic device, and an error detection logic device. The storage element stores a plurality of requestors' information. The winner selection logic device selects a winner requestor among the requestors based on the requestors' information received from a plurality of requestors. The winner selection logic device selects the winner requestor without checking whether there is the soft error in the winner requestor's information.
    Type: Application
    Filed: August 9, 2010
    Publication date: February 9, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Yutaka Sugawara
  • Support for non-locking parallel reception of packets belonging to a single memory reception FIFO
    Patent number: 8086766
    Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-locking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dong Chen, Philip Heidelberger, Valentina Salapura, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • MULTI-PETASCALE HIGHLY EFFICIENT PARALLEL SUPERCOMPUTER
    Publication number: 20110219208
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC).
    Type: Application
    Filed: January 10, 2011
    Publication date: September 8, 2011
    Applicant: International Business Machines Corporation
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Brian Smith, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • SUPPORT FOR NON-LOCKING PARALLEL RECEPTION OF PACKETS BELONGING TO THE SAME RECEPTION FIFO
    Publication number: 20110179199
    Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. A plurality of DMA engine units are configured in a multiprocessor system to operate in parallel, one DMA engine unit for transferring a current packet received at a network reception queue to a memory location in a memory FIFO (rmFIFO) region of a memory. A control unit implements logic to determine whether any prior received packet destined for that rmFIFO is still in a process of being stored in the associated memory by another DMA engine unit of the plurality, and prevent the one DMA engine unit from indicating completion of storing the current received packet in the reception memory FIFO (rmFIFO) until all prior received packets destined for that rmFIFO are completely stored by the other DMA engine units. Thus, there is provided non-blocking support so that multiple packets destined for a single rmFIFO are transferred and stored in parallel to predetermined locations in a memory.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 21, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Philip Heidelberger, Valentina Salapura, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • EMBEDDING GLOBAL BARRIER AND COLLECTIVE IN A TORUS NETWORK
    Publication number: 20110173413
    Abstract: Embodiments of the invention provide a method, system and computer program product for embedding a global barrier and global interrupt network in a parallel computer system organized as a torus network. The computer system includes a multitude of nodes. In one embodiment, the method comprises taking inputs from a set of receivers of the nodes, dividing the inputs from the receivers into a plurality of classes, combining the inputs of each of the classes to obtain a result, and sending said result to a set of senders of the nodes. Embodiments of the invention provide a method, system and computer program product for embedding a collective network in a parallel computer system organized as a torus network. In one embodiment, the method comprises adding to a torus network a central collective logic to route messages among at least a group of nodes in a tree structure.
    Type: Application
    Filed: March 12, 2010
    Publication date: July 14, 2011
    Applicant: International Business Machines Corporation
    Inventors: Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Philip Heidleberger, Robert M. Senger, Valentina Salapura, Burkhard Steinmacher-Burow, Yutaka Sugawara, Todd E. Takken
  • DISTRIBUTED PARALLEL MESSAGING FOR MULTIPROCESSOR SYSTEMS
    Publication number: 20110173399
    Abstract: A method and apparatus for distributed parallel messaging in a parallel computing system. The apparatus includes, at each node of a multiprocessor network, multiple injection messaging engine units and reception messaging engine units, each implementing a DMA engine and each supporting both multiple packet injection into and multiple reception from a network, in parallel. The reception side of the messaging unit (MU) includes a switch interface enabling writing of data of a packet received from the network to the memory system. The transmission side of the messaging unit, includes switch interface for reading from the memory system when injecting packets into the network.
    Type: Application
    Filed: January 26, 2010
    Publication date: July 14, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dong Chen, Philip Heidelberger, Valentina Salapura, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • REPRODUCIBILITY IN A MULTIPROCESSOR SYSTEM
    Publication number: 20110119521
    Abstract: Fixing a problem is usually greatly aided if the problem is reproducible. To ensure reproducibility of a multiprocessor system, the following aspects are proposed: a deterministic system start state, a single system clock, phase alignment of clocks in the system, system-wide synchronization events, reproducible execution of system components, deterministic chip interfaces, zero-impact communication with the system, precise stop of the system and a scan of the system state.
    Type: Application
    Filed: May 5, 2010
    Publication date: May 19, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ralph A. Bellofatto, Dong Chen, Paul W. Coteus, Noel A. Eisley, Alan Gara, Thomas M. Gooding, Rudolf A. Haring, Philip Heidelberger, Gerard V. Kopcsay, Thomas A. Liebsch, Martin Ohmacht, Don D. Reed, Robert M. Senger, Burkhard Steinmacher-Burow, Yutaka Sugawara
  • Image projecting apparatus and image projecting method for use in the same
    Patent number: 7909469
    Abstract: Disclosed herein is an image projecting apparatus, including: a one-dimension type light modulating device for modulating a light in accordance with image information; a projection optical system; and a light deflecting device for deflecting an image light in a direction approximately perpendicular to an extension direction of a one-dimensional image light emitted from the one-dimensional light modulating device; wherein the light deflecting device is composed of a first light deflecting device arranged between the projection optical system and the one-dimension type light modulating device, and a second light deflecting device arranged on an emission side of the projection optical system; the second light deflecting device is detachably mounted.
    Type: Grant
    Filed: April 7, 2008
    Date of Patent: March 22, 2011
    Assignee: Sony Corporation
    Inventors: Izushi Kobayashi, Yutaka Sugawara, Akihiro Kojima, Akira Nakamura, Katsuhisa Ito
  • Screen and image projection apparatus
    Patent number: 7688506
    Abstract: Light emitted from a light source is modulated and projected on a screen. The screen includes a securing member, a diffuser plate supported by the securing member using a plurality of elastic members, where the elastic members are disposed so that the diffuser plate is resiliently displaced in two directions in the plane of the diffuser plate, and a driving unit that moves the diffuser plate with respect to the securing member in the two directions in the plane of the diffuser plate.
    Type: Grant
    Filed: January 22, 2007
    Date of Patent: March 30, 2010
    Assignee: Sony Corporation
    Inventors: Yutaka Sugawara, Hiroki Kikuchi
  • Image projecting apparatus and image projecting method for use in the same
    Publication number: 20080284988
    Abstract: Disclosed herein is an image projecting apparatus, including: a one-dimension type light modulating device for modulating a light in accordance with image information; a projection optical system; and a light deflecting device for deflecting an image light in a direction approximately perpendicular to an extension direction of a one-dimensional image light emitted from the one-dimensional light modulating device; wherein the light deflecting device is composed of a first light deflecting device arranged between the projection optical system and the one-dimension type light modulating device, and a second light deflecting device arranged on an emission side of the projection optical system; the second light deflecting device is detachably mounted.
    Type: Application
    Filed: April 7, 2008
    Publication date: November 20, 2008
    Inventors: Izushi Kobayashi, Yutaka Sugawara, Akihiro Kojima, Akira Nakamura, Katsuhisa Ito