Patents by Inventor Yutaka Takafuji

Yutaka Takafuji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070122998
    Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.
    Type: Application
    Filed: January 26, 2007
    Publication date: May 31, 2007
    Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
  • Publication number: 20070108523
    Abstract: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.
    Type: Application
    Filed: December 28, 2006
    Publication date: May 17, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Yutaka Takafuji
  • Patent number: 7205204
    Abstract: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: April 17, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yasuyuki Ogawa, Yutaka Takafuji
  • Publication number: 20070066035
    Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.
    Type: Application
    Filed: November 16, 2006
    Publication date: March 22, 2007
    Inventors: Steven Droes, Yutaka Takafuji
  • Publication number: 20070063281
    Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.
    Type: Application
    Filed: August 11, 2006
    Publication date: March 22, 2007
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Patent number: 7183179
    Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: February 27, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Steven R. Droes, Yutaka Takafuji
  • Patent number: 7179719
    Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: February 20, 2007
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
  • Patent number: 7119365
    Abstract: A polycrystalline Si thin film and a single crystal Si thin film are formed on an SiO2 film deposited on an insulating substrate. A polycrystalline Si layer is grown by thermally crystallizing an amorphous Si thin film so as to form the polycrystalline Si thin film. A single crystal Si substrate, having (a) an SiO2 film thereon and (b) a hydrogen ion implantation portion therein, is bonded to an area of the polycrystalline Si thin film that has been subjected to etching removal, and is subjected to a heating process. Then, the single crystal Si substrate is divided at the hydrogen ion implantation portion in an exfoliating manner, so as to form the single crystal Si thin film. As a result, it is possible to provide a large-size semiconductor device, having the single crystal Si thin film, whose property is stable, at a low cost.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: October 10, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Patent number: 7071912
    Abstract: A display panel drive circuit and a display panel are provided which are simple in structure but free from initial failure leading to impossibility to perform scanning. The display panel drive circuit of the present invention is structured such that thin film transistors constituting a signal input circuit connected to a circuit outside the display panel are formed in a structure having a dielectric breakdown strength higher than those of thin film transistors constituting other circuits. Specifically, countermeasures are taken by transistor formation in multi-gate structure, gate width broadening, resistance insertion between an input terminal and a transistor or the like. In the present invention, the circuit to which signals are externally inputted or thin film transistors of the same circuit is structured to withstand high voltage, thereby preventing the transistors from being deteriorated by high voltage and occurrence of initial failure while being simple in structure.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: July 4, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Hongyong Zhang, Yosuke Tsukamoto, Yutaka Takafuji, Yasushi Kubota
  • Publication number: 20060073678
    Abstract: A hydrogen (H) exfoliation gettering method is provided for attaching fabricated circuits to receiver substrates. The method comprises: providing a Si substrate; forming a Si active layer overlying the substrate with circuit source/drain (S/D) regions; implanting a p-dopant into the S/D regions; forming gettering regions underling the S/D regions; implanting H in the Si substrate, forming a cleaving plane (peak concentration (Rp) H layer) in the Si substrate about as deep as the gettering regions; bonding the circuit to a receiver substrate; cleaving the Si substrate along the cleaving plane; and binding the implanted H underlying the S/D regions with p-dopant in the gettering regions, as a result of post-bond annealing.
    Type: Application
    Filed: November 16, 2004
    Publication date: April 6, 2006
    Inventors: Steven Droes, Yutaka Takafuji
  • Publication number: 20060068565
    Abstract: A system and method for hydrogen (H) exfoliation are provided for attaching silicon-on-insulator (SOI) fabricated circuits to carrier substrates. The method comprises: providing a SOI substrate, including a silicon (Si) active layer and buried oxide (BOX) layer overlying a Si substrate; forming a circuit in the Si active layer; forming a blocking mask over selected circuit areas; implanting H in the Si substrate; annealing; removing the blocking mask; in response to the H implanting, forming a cleaving plane in the Si substrate; bonding the circuit the top oxide layer to the carrier substrate; and, cleaving the Si substrate. More specifically, the cleaving plane is formed along a horizontal peak concentration (Rp) H layer in the Si substrate and along the buried oxide layer interface.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 30, 2006
    Inventors: Steve Droes, Masao Moriguchi, Yutaka Takafuji
  • Publication number: 20060043485
    Abstract: A method for fabricating a semiconductor device according to the present invention is a method for fabricating a semiconductor device including a substrate layer including a plurality of first regions each having an active region and a plurality of second regions each being provided between adjacent ones of the first region. The fabrication method includes an isolation insulation film formation step of forming an isolation insulation film in each of the second regions so that a surface of the isolation insulation film becomes at the same height as that of a surface of a gate oxide film covering the active region, a peeling layer formation step of forming a peeling layer by ion-implanting hydrogen into the substrate layer after the isolation insulation film formation step, and a separation step of separating part of the substrate layer along the peeling layer.
    Type: Application
    Filed: August 9, 2005
    Publication date: March 2, 2006
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yasumori Fukushima, Masao Moriguchi, Yutaka Takafuji
  • Patent number: 7002659
    Abstract: There is provided a liquid crystal panel in which the brightness of an image is high, and deterioration in display quality due to defects such as uneven display or uneven brightness is suppressed. The liquid crystal panel includes a pixel portion including a plurality of thin film transistors and pixel electrodes formed on a first substrate, a second substrate, a liquid crystal and gap holding members provided between the first substrate and the second substrate, and a microlens array including a plurality of microlenses and provided on a surface of the second substrate, the surface being opposite to the first substrate.
    Type: Grant
    Filed: November 22, 2000
    Date of Patent: February 21, 2006
    Assignees: Semiconductor Energy Laboratory Co., Ltd., Sharp Kabushiki Kaisha
    Inventors: Shunpei Yamazaki, Jun Koyama, Kazuhiko Tamai, Yutaka Takafuji
  • Publication number: 20050282019
    Abstract: A method for manufacturing a semiconductor substrate comprises the steps of: forming a gate oxide film as an insulating layer on the surface of a semiconductor substrate; implanting boron ions for inhibiting the migration of a peeling substance in the semiconductor substrate to form an anti-diffusion layer in the semiconductor substrate; activating boron in the anti-diffusion layer by heat treatment; implanting hydrogen ions into the semiconductor substrate to form a peel layer in part of the semiconductor substrate at a side of the anti-diffusion layer opposite to the gate oxide film; bonding a glass substrate to the surface of the semiconductor substrate where the gate oxide film has been formed; and heat-treating the semiconductor substrate to separate part of the semiconductor substrate along the peel layer.
    Type: Application
    Filed: June 8, 2005
    Publication date: December 22, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasumori Fukushima, Yutaka Takafuji
  • Publication number: 20050245046
    Abstract: The present invention provides a semiconductor substrate, which comprises a singlecrystalline Si substrate which includes an active layer having a channel region, a source region, and a drain region, the singlecrystalline Si substrate including at least a part of a device structure not containing a well-structure or a channel stop region; a gate insulating film formed on the singlecrystalline Si substrate; a gate electrode formed on the gate insulating film; a LOCOS oxide film whose thickness is more than a thickness of the gate insulating film, the LOCOS oxide film being formed on the singlecrystalline Si substrate by surrounding the active layer; and an insulating film formed over the gate electrode and the LOCOS oxide film.
    Type: Application
    Filed: March 23, 2005
    Publication date: November 3, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Yasumori Fukushima, Masao Moriguchi
  • Publication number: 20050236626
    Abstract: In a semiconductor device including an insulative substrate and a thin film device formed thereon, a thin film transistor having a non-single crystalline silicon thin film and a transistor having a single crystalline silicon thin film are intermixed, and a gate electrode film of the thin film transistor having single crystalline silicon is made of a material including a metal whose mass number is larger than that of silicon or a compound containing the metal.
    Type: Application
    Filed: March 24, 2005
    Publication date: October 27, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga, Steven Droes, Masao Moriguchi
  • Publication number: 20050206606
    Abstract: Each of a gate driver and a source driver periodically receives a clock signal and a start pulse, where the start pulse has a certain width and is shifted as shift data in the gate driver or source driver in synchronism with the clock signal. A logic circuit composed of an NAND gate and an inverter receives the start pulse and the shift data, the shift data being the output that is supplied after a predetermined delay from the last stage with respect to the shift direction. The output of the inverter is used to test scanning circuits. This provides a display device and a scanning circuit testing method, which enable the scanning circuits to be judged both surely and quickly, without increasing the area or complexity of the circuit.
    Type: Application
    Filed: May 5, 2005
    Publication date: September 22, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Katsunori Shirai, Akira Shibazaki
  • Publication number: 20050173761
    Abstract: A semiconductor device includes a substrate with an insulating surface and a single crystal semiconductor layer, which is bonded to the insulating surface of the substrate. The device further includes a first insulating layer, which is provided between the insulating surface of the substrate and the single crystal semiconductor layer, and a second insulating layer, which has been deposited on the entire insulating surface of the substrate except an area in which the first insulating layer is present.
    Type: Application
    Filed: February 1, 2005
    Publication date: August 11, 2005
    Applicant: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Takashi Itoga
  • Patent number: 6909304
    Abstract: Each of a gate driver and a source driver periodically receives a clock signal and a start pulse, where the start pulse has a certain width and is shifted as shift data in the gate driver or source driver in synchronism with the clock signal. A logic circuit composed of an NAND gate and an inverter receives the start pulse and the shift data, the shift data being the output that is supplied after a predetermined delay from the last stage with respect to the shift direction. The output of the inverter is used to test scanning circuits. This provides a display device and a scanning circuit testing method, which enable the scanning circuits to be judged both surely and quickly, without increasing the area or complexity of the circuit.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: June 21, 2005
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yutaka Takafuji, Katsunori Shirai, Akira Shibazaki
  • Publication number: 20050087739
    Abstract: In a semiconductor device including a monocrystalline thin film transistor 16a that has been formed on a monocrystalline Si wafer 100 and then is transferred to a insulating substrate 2, LOCOS oxidization is performed with respect to the element-isolation region of the monocrystalline Si wafer 100 so as to create a field oxide film (SiO2 film) 104, and a marker 107 is formed on the field oxide film 104. With this structure, alignment of components may be performed based on a gate electrode 106 upon or after the transfer step.
    Type: Application
    Filed: October 14, 2004
    Publication date: April 28, 2005
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: Yasuyuki Ogawa, Yutaka Takafuji