Abstract: A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2, wherein an electrostatic capacity C1 of the first capacitance section and an electrostatic capacity C2 of the second capacitance section are different, and L1/L2=0.8 to 1.2.

Abstract: A stretchable wiring board that includes: a stretchable substrate; a first stretchable wiring extending in a length direction on a main surface side of the stretchable substrate; and a second stretchable wiring extending in the length direction on the main surface side of the stretchable substrate, the second stretchable wiring having a first portion with a first region overlapping on top of the first stretchable wiring on an end portion side of the first stretchable wiring, and a width of the first portion of the second stretchable wiring in a width direction orthogonal to the length direction is smaller than a width of the first stretchable wiring.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface that face each other in a thickness direction, the first main surface containing a trench; an insulation layer on a surface of the trench; a first electrode layer on the insulation layer; a first dielectric layer on the first electrode layer; and a second electrode layer on the first dielectric layer, in which a thickness (L1) of the insulation layer, a thickness (L2) of the first electrode layer, and a thickness (L4) of the second electrode layer satisfy L1>L2>L4.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface facing each other in a thickness direction, the first main surface including a trench. The trench has a predetermined depth in the thickness direction and has a substantially wedge shape that has a first side surface and a second side surface that face each other and are not parallel to each other, and a first end surface and a second end surface that face each other and are substantially parallel to each other. The first side surface and the second side surface intersect each other at a line, or extension surfaces of the first side surface and the second side surface extended in the thickness direction intersect each other at a line, and the line extends in a first direction that does not align with a cleavage plane of the semiconductor substrate.

Abstract: A semiconductor device that includes a semiconductor substrate; a first capacitance section on the semiconductor substrate, the first capacitance section including a first electrode layer, a first dielectric layer, and a second electrode layer; a second capacitance section on the semiconductor substrate, the second capacitance section including a third electrode layer, a second dielectric layer, and a fourth electrode layer; a first external electrode; a second external electrode; a first lead wire led out from the first capacitance section to the first external electrode and having an inductance L1; and a second lead wire led out from the second capacitance section to the second external electrode and having an inductance L2, wherein an electrostatic capacity C1 of the first capacitance section and an electrostatic capacity C2 of the second capacitance section are different, and L1/L2=0.8 to 1.2.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface facing each other in a thickness direction, the first main surface including a trench. The trench has a predetermined depth in the thickness direction and has a substantially wedge shape that has a first side surface and a second side surface that face each other and are not parallel to each other, and a first end surface and a second end surface that face each other and are substantially parallel to each other. The first side surface and the second side surface intersect each other at a line, or extension surfaces of the first side surface and the second side surface extended in the thickness direction intersect each other at a line, and the line extends in a first direction that does not align with a cleavage plane of the semiconductor substrate.

Abstract: A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface that face each other in a thickness direction, the first main surface containing a trench; an insulation layer on a surface of the trench; a first electrode layer on the insulation layer; a first dielectric layer on the first electrode layer; and a second electrode layer on the first dielectric layer, in which a thickness (L1) of the insulation layer, a thickness (L2) of the first electrode layer, and a thickness (L4) of the second electrode layer satisfy L1>L2>L4.

Abstract: A composite electronic component that includes an insulation substrate having a principal surface; a thin-film capacitor on the principal surface of the insulation substrate; a laminated insulation protection layer covering the thin-film capacitor; a first extended wiring in the insulation protection layer and connected to the thin-film capacitor; a first resin layer on the insulation protection layer, first and second thin-film resistors in the first resin layer; a through-hole penetrating the first resin layer in a thickness direction thereof so as to expose the first extended wiring; a first rewiring in the first resin layer and connected to the first extended wiring through the through-hole; and a second resin layer on the first resin layer. The interior of the through-hole is filled with the second resin layer, and the through-hole does not overlap the thin-film capacitor.

Abstract: An ESD-protective-function-equipped composite electronic component is provided that includes multiple Zener diodes formed from first and second semiconductor layers. Moreover, the second semiconductor layers are disposed on an insulating substrate and in the same plane. The electronic component includes electrodes extending from each of the Zener diodes and one or more thin-film circuit element connected in series between a pair of the electrodes.

Abstract: A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.

Abstract: An ESD-protective-function-equipped composite electronic component is provided that includes multiple Zener diodes formed from first and second semiconductor layers. Moreover, the second semiconductor layers are disposed on an insulating substrate and in the same plane. The electronic component includes electrodes extending from each of the Zener diodes and one or more thin-film circuit element connected in series between a pair of the electrodes.

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract: A semiconductor package includes an interposer, a semiconductor element installed on a first surface of the interposer, bumps formed on a second surface of the interposer, and a chip component installed on the second surface of the interposer. The interposer is a silicon interposer; the semiconductor element is flip-chip mounted on the first surface of the interposer; the chip component is a thin film passive element formed by carrying out a thin film process on a silicon substrate, and a pad being formed on one surface of the thin film passive element; and the pad of the chip component is connected to a land formed on the second surface of the interposer using a conductive bonding material. According to this structure, the reliability of a bond between the interposer and the chip component of the semiconductor package can be ensured while achieving a small size.

Abstract: A composite electronic component that includes an insulation substrate having a principal surface; a thin-film capacitor on the principal surface of the insulation substrate; a laminated insulation protection layer covering the thin-film capacitor; a first extended wiring in the insulation protection layer and connected to the thin-film capacitor; a first resin layer on the insulation protection layer, first and second thin-film resistors in the first resin layer; a through-hole penetrating the first resin layer in a thickness direction thereof so as to expose the first extended wiring; a first rewiring in the first resin layer and connected to the first extended wiring through the through-hole; and a second resin layer on the first resin layer. The interior of the through-hole is filled with the second resin layer, and the through-hole does not overlap the thin-film capacitor.

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer 22. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract: A dielectric thin film element having a high humidity resistance is provided. A dielectric thin film element includes a capacitance section having a dielectric layer and a pair of electrode layers formed on the respective upper and lower surfaces of the dielectric layer. Furthermore, a protection layer is provided on the capacitance section, a pair of interconnect layers are drawn out to an upper surface of the protection layer, and external electrodes are formed to be electrically connected to the interconnect layers. Further, first surface metal layers cover a portion of the interconnect layers that extends along the inner surface of the openings and second surface metal layers are formed at end of the first surface metal layers.

Abstract: A piezoelectric device that includes a piezoelectric film, which is formed by a sputtering method and which has a columnar structure, and electrodes disposed in contact with the piezoelectric film. The piezoelectric film has a composition containing an element which can substitute Nb and has an oxidation number of 2 or more and less than 5 when oxidized in a proportion of 3.3 mol or less relative to 100 mol of potassium sodium niobate represented by a general formula (K1-xNax)NbO3, where 0<x<1.

Abstract: An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component.

Abstract: A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.

Abstract: A method for producing a thin film laminated capacitor that makes it possible to reduce the number of operations for etching its electrode layers and its dielectric layers. On a substrate, a capacitor part is formed wherein n electrode layers and (n?1) dielectric layers are alternately laminated onto each other, wherein n is 4 or more. The capacitor part is etched from the same side k times. In any ith etching operation, through holes are formed in an amount corresponding to respective ai layers of the electrode layers and the dielectric layers. At least one of ai's is set to 2 or more, and k is made smaller than n?1, thereby making it possible to make the 2nd to nth layers of the electrode layers from the etching starting side exposed at the bottom surfaces of the through holes.