Abstract: In an embodiment, a semiconductor integrated circuit device includes a driver circuit that drives a transmission line, an output terminal coupled to the output of the driver circuit, and a variable-impedance circuit. The variable-impedance circuit is coupled, for example, between the driver circuit and the output terminals for series-termination of the transmission line.

Abstract: In an embodiment, a semiconductor integrated circuit device includes a driver circuit that drives a transmission line, an output terminal coupled to the output of the driver circuit, and a variable-impedance circuit. The variable-impedance circuit is coupled, for example, between the driver circuit and the output terminals for series-termination of the transmission line.

Abstract: In an embodiment, a semiconductor integrated circuit device includes a driver circuit that drives a transmission line, an output terminal coupled to the output of the driver circuit, and a variable-impedance circuit. The variable-impedance circuit is coupled, for example, between the driver circuit and the output terminals for series-termination of the transmission line.

Abstract: A chopper comparator has inverters in input and output stages including NMOS transistors to control connection and disconnection of an inverter circuit of each inverter. During a non-operation period of the chopper comparator, parts of the inverters are disconnected form the ground based on a signal supplied to gates of the NMOS transistors.

Abstract: A chopper comparator has inverters (1,2) in input and output stages including NMOS transistors (M3,M6) to control the connection and disconnection of an inverter circuit forming each inverter (1,2). During a non-operation period of the chopper comparator, circuits formed in the inverters (1,2) are disconnected form the ground based on a PS signal to be supplied to gates of the NMOS transistors (M3,M6).

Abstract: In a semiconductor integrated circuit having a gate array structure, within a cell, isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power supply wiring section, or between the intra-cell gate output terminal and an intra-cell ground wiring section. Isolation transistors are disposed in series between an extra-cell gate output terminal and an extra-cell power supply wiring section between cells, or between the extra-cell gate output terminal and an extra-cell ground wiring section.

Abstract: In a semiconductor substrate, at least one diffusion region exists between resistors on an element isolation layer, and the resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal.

Abstract: A semiconductor integrated circuit including circuit groups and driving the circuit groups with respective power supply voltages, digital-to-analog converters that supply the power supply voltages to the circuit groups, and delay measurement circuits that measure delays of circuit element of the circuit groups. This semiconductor integrated circuit includes a central processing unit that establishes settings of registers based on measurements by the delay measurement circuits to control each of the power supply voltages.

Abstract: In the semiconductor integrated circuit of a gate array structure, within a cell, a plurality of isolation transistors are disposed in series between an intra-cell gate output terminal and an intra-cell power supply wiring section, or between the intra-cell gate output terminal and an intra-cell ground wiring section. While between cells, a plurality of isolation transistors are disposed in series between an extra-cell gate output terminal and an extra-cell power supply wiring section, or between the extra-cell gate output terminal and an extra-cell ground wiring section.

Abstract: At least one diffusion region exists between a plurality of resistors formed on an element isolation layer, and the plurality of resistors and the diffusion regions are arranged such that all distances between the respective resistors and the diffusion regions around the corresponding resistors are equal to each other.

Abstract: A method of doping a compound semiconductor layer n-type during epitaxial growth of the compound semiconductor layer includes supplying source materials including respective elements of a compound semiconductor material to a heated monocrystalline substrate, epitaxially growing a layer of the compound semiconductor material on the heated substrate and, simultaneously, supplying SiI.sub.4 as a dopant source material including silicon to the heated substrate, incorporating silicon as a dopant impurity producing n-type conductivity into the compound semiconductor layer during the epitaxial growth.