Patents by Inventor YUTAO FANG

YUTAO FANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11966900
    Abstract: A transaction record is created showing a purchase transaction of a customer. A CV profile showing a list of items in the transaction obtained from images is also obtained. The items in the transaction record are compared to items on the list. When there is a discrepancy, an action to take is determined.
    Type: Grant
    Filed: July 16, 2020
    Date of Patent: April 23, 2024
    Assignee: Walmart Apollo, LLC
    Inventors: Zhichun Xiao, Lingfeng Zhang, Jon Hammer, Joseph Duffy, Yao Liu, Sicong Fang, Xiang Yao, Pingyuan Wang, Yu Tao, Tianyi Mao, Yutao Tang, Feiyun Zhu, Han Zhang, Chunmei Wang, Pingjian Yu, Muzzammil Afroz, Haining Liu
  • Publication number: 20230104038
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x decreases and z increases along a direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Application
    Filed: November 21, 2022
    Publication date: April 6, 2023
    Inventors: BOTING LIU, YUTAO FANG, SHUAI CHEN, NIENTZE YEH, FUCHIN CHANG
  • Patent number: 11508837
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: November 22, 2022
    Assignee: Xiamen Sanan Integrated Circuit Co., Ltd.
    Inventors: Yutao Fang, Boting Liu, Nien-Tze Yeh, Kaixuan Zhang
  • Publication number: 20200350426
    Abstract: An epitaxial structure for a high-electron-mobility transistor includes a substrate, a nucleation layer, a buffer layered unit, a channel layer, and a barrier layer sequentially stacked on one another in such order. The buffer layered unit includes at least one multiple quantum well structure containing a plurality of p-i-n heterojunction stacks. Each of the p-i-n heterojunction stacks includes p-type, i-type, and n-type layers which are alternately stacked along a direction away from the nucleation layer, and which are made of materials respectively represented by chemical formulas of AlxGa(1-x)N, AlyGa(1-y)N, and AlzGa(1-z)N. For each of the p-i-n heterojunction stacks, x gradually decreases and z gradually increases along the direction away from the nucleation layer, and y is consistent and ranges from 0 to 0.7.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: YUTAO FANG, BOTING LIU, NIEN-TZE YEH, KAIXUAN ZHANG