Patents by Inventor Yuto Hosogaya

Yuto Hosogaya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220114147
    Abstract: An information processing apparatus in which data is accessed every predetermined data amount, wherein when writing data transmitted from a host system side, in the case where the data is presumed to be continuous data constituting a single file, metadata indicating that the data from the host system side is continuous data is written along with the data.
    Type: Application
    Filed: December 3, 2019
    Publication date: April 14, 2022
    Inventors: SHINGO ASO, YUTO HOSOGAYA
  • Publication number: 20210224001
    Abstract: The efficiency of processing is increases even in a case where an area release notification issued to expressly specify release of an unnecessary area from a host side is inconsistent with a management unit of a storage. The storage controller receives at least one area release request for the storage from a host computer. Until predetermined conditions are met after the receipt of the area release request, the storage controller causes the storage to suspend a process on the area release request. When the predetermined conditions are met, the storage controller causes the storage to execute the process on the area release request.
    Type: Application
    Filed: May 17, 2019
    Publication date: July 22, 2021
    Inventor: YUTO HOSOGAYA
  • Patent number: 10602361
    Abstract: A storage device of the disclosure includes: a storage section that stores data; a communication section that performs wireless communication with one or a plurality of electronic apparatuses; an interface section that performs exchange of the data with a host apparatus; and a control section that determines a distance to each of the electronic apparatuses through the wireless communication, and controls access to the storage section by the host apparatus, on the basis of the distance and whether the host apparatus is accessing the storage section.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: March 24, 2020
    Assignee: Sony Corporation
    Inventors: Yuto Hosogaya, Shingo Aso, Yuya Ishikawa
  • Publication number: 20180124610
    Abstract: A storage device of the disclosure includes: a storage section that stores data; a communication section that performs wireless communication with one or a plurality of electronic apparatuses; an interface section that performs exchange of the data with a host apparatus; and a control section that determines a distance to each of the electronic apparatuses through the wireless communication, and controls access to the storage section by the host apparatus, on the basis of the distance and whether the host apparatus is accessing the storage section.
    Type: Application
    Filed: April 22, 2016
    Publication date: May 3, 2018
    Inventors: Yuto Hosogaya, Shingo Aso, Yuya Ishikawa
  • Patent number: 9916103
    Abstract: A memory control device includes a control unit that performs data write/read control on a nonvolatile memory having at least a first area and a second area. In a case where writing sets of data into the first area, the control unit temporarily writes the sets of data into the second area. In a case where copying the respective sets of data written into the second area into the first area, the control unit sets a flag indicating whether the copying of the sets of data into the first area has been completed.
    Type: Grant
    Filed: April 21, 2015
    Date of Patent: March 13, 2018
    Assignee: SONY CORPORATION
    Inventor: Yuto Hosogaya
  • Publication number: 20170046084
    Abstract: A memory control device includes a control unit that performs data write/read control on a nonvolatile memory having at least a first area and a second area. In a case where writing sets of data into the first area, the control unit temporarily writes the sets of data into the second area. In a case where copying the respective sets of data written into the second area into the first area, the control unit sets a flag indicating whether the copying of the sets of data into the first area has been completed.
    Type: Application
    Filed: April 21, 2015
    Publication date: February 16, 2017
    Applicant: SONY COPORATION
    Inventor: YUTO HOSOGAYA
  • Patent number: 8885406
    Abstract: A memory device includes: a plurality of nonvolatile memory sections configured to allow one memory cell to record data of a plurality of bits, and to include a corresponding number of pages to the plurality of bits in accordance with a plurality of the memory cells as a write control unit; and a control section configured to control writing and reading data to and from the plurality of nonvolatile memory sections, wherein among the plurality of nonvolatile memory sections, if data is written into one of the nonvolatile memory sections, the data is written for each page in sequence from a low-order page to a high-order page, and when the data is written into the low-order page, control is performed such that the data to be written into the low-order page is written into any area of the other of the nonvolatile memory sections at same timing.
    Type: Grant
    Filed: April 19, 2013
    Date of Patent: November 11, 2014
    Assignee: Sony Corporation
    Inventors: Yuto Hosogaya, Shingo Aso
  • Publication number: 20130286731
    Abstract: A memory device includes: a plurality of nonvolatile memory sections configured to allow one memory cell to record data of a plurality of bits, and to include a corresponding number of pages to the plurality of bits in accordance with a plurality of the memory cells as a write control unit; and a control section configured to control writing and reading data to and from the plurality of nonvolatile memory sections, wherein among the plurality of nonvolatile memory sections, if data is written into one of the nonvolatile memory sections, the data is written for each page in sequence from a low-order page to a high-order page, and when the data is written into the low-order page, control is performed such that the data to be written into the low-order page is written into any area of the other of the nonvolatile memory sections at same timing.
    Type: Application
    Filed: April 19, 2013
    Publication date: October 31, 2013
    Applicant: Sony Corporation
    Inventors: Yuto Hosogaya, Shingo Aso
  • Publication number: 20120278539
    Abstract: A memory apparatus includes: a plurality of flash memory sections connected to a common data line; and a control section configured to perform control for data read/write on the plurality of flash memory sections, wherein the control section performs control so as to give a read instruction to a first flash memory section among the plurality of flash memory sections to output read data from the first flash memory section onto the common data line, and to give a write instruction to a second flash memory section other than the first flash memory section to write the read data obtained on the common data line into the second flash memory section with timing in accordance with timing of outputting the read data from the first flash memory section.
    Type: Application
    Filed: March 16, 2012
    Publication date: November 1, 2012
    Applicant: SONY CORPORATION
    Inventor: Yuto Hosogaya