Abstract: The present invention belongs to animal experiments field, disclosed a single factor modeling-constraint method and device for mice chronic fatigue syndrome, the modeling-constraint method is specifically using mineral water bottle to restraint mice; the mineral water bottle is divided into upper, middle and lower parts; the body of mineral water bottle is uniformly drilled for mice to breathe; the inner of the mineral water bottle is blocked by a cardboard to reduce the move space of mice; cover the mice through the divided bottle; one end of the opening is tightly attach to the wall, the other end is tightly attach to the mice feeding box, and keeping 30 minutes to restraint. The present invention utilizes mineral water bottle to make three simple restraint tube, not only saves the costs of experiment, but also turns waste into treasure, which is a simple operation, and increases the possibility of the experiment.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: Disclosed is a thin-film transistor. The thin-film transistor includes: a substrate; a first gate, a first gate insulation layer, a semiconductor layer, an etching stop layer, and the second gate stacked on a surface of the substrate, in which the semiconductor layer has a thickness of 200 nm-2000 nm; the etching stop layer includes a first via and a second via formed therein; and the first via and the second via are arranged to each correspond to the semiconductor layer; and a source and a drain respectively extending through the first via and the second via to connect to the semiconductor layer. The thin-film transistor has an increased ON-state current and switching speed.

Abstract: A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. An isolation layer with a flat top surface is sandwiched between a transparent electrode and a pixel electrode to form a transparent capacitor.

Abstract: A manufacturing method of array substrates, an array substrate, and a display panel are disclosed. The manufacturing method of the array substrate includes: forming a first electrode and a gate electrode on a substrate in sequence; forming an insulation layer, a semiconductor layer and a dielectric layer on the substrates in sequence and forming a first through hole, a second through hole and a third through hole; forming a source electrode, a drain electrode, a second electrode and a third electrode on the dielectric layer, wherein the source electrode and the drain electrode connect to the semiconductor layer respectively, the second electrode connects to the first electrode and the third electrode connects with the drain electrode. In this way, the number of the masks needed during the manufacturing process is decreased. In addition, the manufacturing process is simplified and the cost is reduced.

Abstract: An LTPS pixel unit and a manufacturing method. The method includes following steps: forming a buffering layer on the substrate; forming a semiconductor pattern and a common electrode pattern which are disposed with an interval on the buffering layer; sequentially forming a first insulation layer, a gate electrode pattern and a second insulation layer on the semiconductor pattern; forming a source electrode pattern and a drain electrode pattern on the second insulation layer, wherein, the source electrode pattern and the drain electrode pattern electrically contact with the semiconductor pattern through a first contact hole at the first insulation layer and the second insulation layer; and forming a pixel electrode pattern on the second insulation layer, wherein, the pixel electrode pattern electrically contacts with the source electrode pattern or the drain electrode pattern. Accordingly, the present invention can save the cost and increase process yield.

Abstract: A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. A transparent electrode, a pixel electrode and a flat isolation layer sandwiched between the transparent electrode and the pixel electrode construct a transparent capacitor.

Abstract: A pixel circuit and a pixel structure having high aperture ratio are provided. A first gate electrode, a layer including a first source electrode and a first drain electrode, and an etching stopper layer, a first semiconductor layer, and a gate isolation layer sandwiched between the first gate electrode and the layer of the first source electrode and the first drain electrode construct a first thin film transistor. A second gate electrode, a layer including a second source electrode and a second drain electrode, and an etching stopper layer, a second semiconductor layer, and the gate isolation layer sandwiched between the second gate electrode and the layer of the second source electrode and the second drain electrode construct a second thin film transistor. A transparent electrode, a pixel electrode and a flat isolation layer sandwiched between the transparent electrode and the pixel electrode construct a transparent capacitor.

Abstract: The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.

Abstract: An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.

Abstract: Disclosed are a method for manufacturing a TFT substrate having storage capacitors and the TFT substrate. The method includes: (1) forming a gate terminal and a first metal electrode; (2) forming a gate insulation layer and a gate insulation layer through-hole; (3) forming an oxide semiconductor layer; (4) subjecting a portion of the oxide semiconductor layer to N-type heavy doping to form a first conductor electrode thereby constituting a first storage capacitor; (5) forming an etch stop layer and a first etch stop layer through-hole; (6) forming source/drain terminals and a second metal electrode, thereby constituting a second storage capacitor connected in parallel to the first capacitor; (7) forming a protection layer, a protection layer through-hole, and a second etch stop layer through-hole; and (8) forming a pixel electrode and a second conductor electrode, thereby constituting a third storage capacitor connected in parallel to the second capacitor.

Abstract: A manufacturing method of array substrates, an array substrate, and a display panel are disclosed. The manufacturing method of the array substrate includes: forming a first electrode and a gate electrode on a substrate in sequence; forming an insulation layer, a semiconductor layer and a dielectric layer on the substrates in sequence and forming a first through hole, a second through hole and a third through hole; forming a source electrode, a drain electrode, a second electrode and a third electrode on the dielectric layer, wherein the source electrode and the drain electrode connect to the semiconductor layer respectively, the second electrode connects to the first electrode and the third electrode connects with the drain electrode. In this way, the number of the masks needed during the manufacturing process is decreased. In addition, the manufacturing process is simplified and the cost is reduced.

Abstract: The disclosure is related to a method for forming a test pad between adjacent transistors regions, comprising forming a plurality of transistor regions in an array on a glass substrate, wherein each of the transistor region comprises a first transistor region and a second transistor region arranged oppositely; and forming a plurality of test pads between the first transistor region and the second transistor region. The disclosure is further related to a method for array test on the adjacent transistor regions using the test pad formed by the above method. A common test pad formed between the adjacent transistor regions of each transistor region group is employed by the disclosure to perform array test on the adjacent transistor regions. Thus the size of the adjacent fringe region of each transistor region may be reduced to facilitate achieving narrow frame of a display.

Abstract: An LTPS array substrate includes a plurality of LTPS thin-film transistors and a bottom transparent conductive layer, a protective layer, and a top transparent conductive layer. Each LTPS thin-film transistor includes a substrate, a patternized light shield layer, a buffering layer, a patternized poly-silicon layer, a gate insulation layer, a gate line, and a common electrode line, an insulation layer, a drain and a source, and a planarization layer that are formed to sequentially stack on each other. The light shield layer covers the scan line and the source/drain. A patternized third metal layer is between the bottom transparent conductive layer and the protective layer and includes a first zone and a second zone intersecting the first zone. The first zone shields the source line. A portion of the second zone overlaps a side portion of the light shield layer that is close to the source/drain electrode.

Abstract: The present invention provides a pixel structure having high aperture ratio and circuit. The first gate (21), the first source/the first drain (61), and the etching stopper layer (5), the first semiconductor layer (41), the gate isolation layer (3) sandwiched in-between of the pixel structure having high aperture ratio construct a first thin film transistor (TFT1); the second gate (22), the second source/the second drain (62), and the etching stopper layer (5), the second semiconductor layer (42), the gate isolation layer (3) sandwiched in between construct a second thin film transistor (TFT2); the transparent electrode (8), the pixel electrode (10) and the flat isolation layer (9)sandwiched in-between construct a transparent capacitor (C), and the transparent capacitor (C) constructs an activation area part of the pixel structure which is capable of increasing the activation area of the pixel and raising the aperture ratio to increase the display brightness and reduce the power consumption.

Abstract: The present invention provides a method for manufacturing a TFT substrate having storage capacitors and the TFT substrate.

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: The present invention discloses an array substrate manufacturing method, an array substrate and a display panel, and the method comprises: forming a gate electrode and a first electrode which is transparent on the substrate; forming an isolated layer on the substrate, and covering the isolated layer on the gate electrode and the first electrode; forming a semiconductor layer on the isolated layer; forming a medium layer on the semiconductor layer, and providing a first via hole, a second via hole and a third via hole; forming a source electrode, a drain electrode, and a second electrode on the medium layer, the source electrode and the drain electrode are connected to the semiconductor layer respectively through the first via hole and the second via hole, and the second electrode is connected to the first electrode through the third via hole to form a storage capacitance; forming a third electrode which is transparent on the medium layer, and the third electrode is connected to the drain electrode to form a p