Patents by Inventor Yuuichi Hirano
Yuuichi Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7838349Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.Type: GrantFiled: June 2, 2008Date of Patent: November 23, 2010Assignee: Renesas Electronics CorporationInventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
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Patent number: 7741679Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.Type: GrantFiled: October 3, 2007Date of Patent: June 22, 2010Assignee: Renesas Technology Corp.Inventors: Yasuo Yamaguchi, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
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Patent number: 7723790Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.Type: GrantFiled: September 11, 2008Date of Patent: May 25, 2010Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
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Patent number: 7675122Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.Type: GrantFiled: August 15, 2007Date of Patent: March 9, 2010Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Takashi Ipposhi, Shigeto Maegawa, Koji Nii
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Patent number: 7608879Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).Type: GrantFiled: August 17, 2007Date of Patent: October 27, 2009Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Takashi Ipposhi, Yuuichi Hirano
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Patent number: 7598570Abstract: A semiconductor device according to the present invention is provided with an SOI substrate, an active region, a first insulating film (complete separation insulating film), a second insulating film (partial separation insulating film), and a contact portion. Here, the active region is formed within the surface of the SOI layer. In addition, the first insulating film is formed on one side of the active region from the surface of SOI layer to the buried insulating film. In addition, the second insulating film is formed on the other side of the active region from the surface of SOI layer to a predetermined depth that does not reach the buried insulating film. In addition, the contact portion is provided toward the side where the first insulating film exists, off the center of the active region in a plan view.Type: GrantFiled: October 17, 2005Date of Patent: October 6, 2009Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Takashi Ipposhi
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Patent number: 7541644Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).Type: GrantFiled: March 8, 2004Date of Patent: June 2, 2009Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Shigenobu Maeda, Takuji Matsumoto, Takashi Ipposhi, Shigeto Maegawa
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Patent number: 7482658Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.Type: GrantFiled: February 22, 2007Date of Patent: January 27, 2009Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
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Publication number: 20090014797Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.Type: ApplicationFiled: September 11, 2008Publication date: January 15, 2009Applicant: Renesas Technology Corp.Inventors: Yuuichi HIRANO, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
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Publication number: 20080315313Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.Type: ApplicationFiled: October 3, 2007Publication date: December 25, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuo YAMAGUCHI, Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Takuji Matsumoto, Shoichi Miyamoto
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Publication number: 20080274596Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.Type: ApplicationFiled: June 2, 2008Publication date: November 6, 2008Applicant: Renesas Technology CorporationInventors: Takuji MATSUMOTO, Toshiaki Iwamatsu, Yuuichi Hirano
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Patent number: 7439587Abstract: An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.Type: GrantFiled: February 22, 2007Date of Patent: October 21, 2008Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Shigeto Maegawa, Toshiaki Iwamatsu, Takuji Matsumoto, Shigenobu Maeda, Yasuo Yamaguchi
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Publication number: 20080211035Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.Type: ApplicationFiled: August 15, 2007Publication date: September 4, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yuuichi Hirano, Takashi Ipposhi, Shigeto Maegawa, Koji Nii
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Patent number: 7393731Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.Type: GrantFiled: June 21, 2005Date of Patent: July 1, 2008Assignee: Renesas Technology Corp.Inventors: Takuji Matsumoto, Toshiaki Iwamatsu, Yuuichi Hirano
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Publication number: 20080128810Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: December 21, 2007Publication date: June 5, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
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Publication number: 20080128814Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: December 21, 2007Publication date: June 5, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
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Patent number: 7382026Abstract: A contact connected to a word line is formed on a gate electrode of an access transistor of an SRAM cell. The contact passes through an element isolation insulating film to reach an SOI layer. A body region of a driver transistor and that of the access transistor are electrically connected with each other through the SOI layer located under the element isolation insulating film. Therefore, the access transistor is in a DTMOS structure having the gate electrode connected with the body region through the contact, which in turn is also electrically connected to the body region of the driver transistor. Thus, operations can be stabilized while suppressing increase of an area for forming the SRAM cell.Type: GrantFiled: August 15, 2007Date of Patent: June 3, 2008Assignee: Renesas Technology Corp.Inventors: Yuuichi Hirano, Takashi Ipposhi, Shigeto Maegawa, Koji Nii
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Publication number: 20080067593Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: ApplicationFiled: October 31, 2007Publication date: March 20, 2008Applicant: RENESAS TECHNOLOGY CORP.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi
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Patent number: 7339238Abstract: It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P? well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P? well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).Type: GrantFiled: August 28, 2006Date of Patent: March 4, 2008Assignee: Renesas Technology Corp.Inventors: Shigenobu Maeda, Takashi Ipposhi, Yuuichi Hirano
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Patent number: 7332776Abstract: A partial isolation insulating film provided between MOS transistors in an NMOS region and a PMOS region, respectively, has a structure in which a portion protruding upward from a main surface of an SOI layer is of greater thickness than a trench depth, namely, a portion (isolation portion) extending below the surface of the SOI layer, and the SOI layer under the partial isolation insulating film is of greater thickness than the isolation portion.Type: GrantFiled: July 17, 2007Date of Patent: February 19, 2008Assignee: Renesas Technology Corp.Inventors: Toshiaki Iwamatsu, Yuuichi Hirano, Takashi Ipposhi