Patents by Inventor Yuuichi Hotta

Yuuichi Hotta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device having signal line and reference potential planes separated by a vertical gap
    Patent number: 7576629
    Abstract: A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: August 18, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Yuuichi Hotta
  • Input/output circuit and semiconductor integrated circuit
    Patent number: 7330502
    Abstract: An input/output circuit includes a reference clock generator configured to generate a reference clock. A signal transmitter is configured to transmit serial data in synchronization with one of the reference clock and a test clock. A signal-receiving circuit is configured to receive the serial data, and to generate a converted signal from the serial data. A test circuit is configured to detect an error between each phase of the converted signal and the test clock when the signal transmitter operates in synchronization with the test clock.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: February 12, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yuuichi Hotta
  • Semiconductor device having signal line and reference potential plane
    Publication number: 20060146135
    Abstract: A semiconductor device according to the one embodiment of the present invention comprises a signal line; and a reference potential plane which is separated from the signal line and opposed to the signal line, the reference potential plane being provided with a discontinuous region in a portion intersecting with the signal line, as a delay element to be added to the signal line.
    Type: Application
    Filed: December 7, 2005
    Publication date: July 6, 2006
    Inventors: Tetsu Nagamatsu, Yuuichi Hotta
  • Input/output circuit and semiconductor integrated circuit
    Publication number: 20040250180
    Abstract: An input/output circuit includes a reference clock generator configured to generate a reference clock. A signal transmitter is configured to transmit serial data in synchronization with one of the reference clock and a test clock. A signal-receiving circuit is configured to receive the serial data, and to generate a converted signal from the serial data. A test circuit is configured to detect an error between each phase of the converted signal and the test clock when the signal transmitter operates in synchronization with the test clock.
    Type: Application
    Filed: April 14, 2004
    Publication date: December 9, 2004
    Inventor: Yuuichi Hotta