Patents by Inventor Yuuichi Kohno

Yuuichi Kohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing semiconductor device including wiring layout and semiconductor device
    Patent number: 8450858
    Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.
    Type: Grant
    Filed: April 30, 2010
    Date of Patent: May 28, 2013
    Assignee: Ricoh Company, Ltd.
    Inventors: Takuya Takahashi, Fumihiro Fuchino, Yuuichi Kohno, Masanori Miyata
  • Chemical mechanical polishing method and chemical mechanical polishing device
    Patent number: 8116894
    Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: February 14, 2012
    Assignee: Ricoh Company, Ltd.
    Inventors: Masanori Miyata, Taro Usami, Koichi Sogawa, Kenji Nishihara, Tadao Uehara, Shisyo Chin, Hiroaki Teratani, Akinori Suzuki, Yuuichi Kohno, Tetsuya Okada, Tohru Haruki
  • Method Of Manufacturing Semiconductor Device Including Wiring Layout And Semiconductor Device
    Publication number: 20100295184
    Abstract: A method of manufacturing a semiconductor device having a first wiring layer, a first interlayer insulating film, a second interlayer insulating film, a third interlayer insulating film, and a second wiring layer, in which the method includes depositing the second wiring layer on the third interlayer insulating film and, where the widths of first wiring layer and the second wiring layer are 10.0 ?m or greater, executing one of etching the second wiring layer to set a width of 1.0 ?m or greater in a portion where the first wiring layer and the second wiring layer overlap and etching the second wiring layer to seta horizontal distance of 2.0 ?m or greater between adjacent portions of the first wiring layer and the second wiring layer.
    Type: Application
    Filed: April 30, 2010
    Publication date: November 25, 2010
    Applicant: RICOH COMPANY, LTD.
    Inventors: Takuya Takahashi, Fumihiro Fuchino, Yuuichi Kohno, Masanori Miyata
  • CHEMICAL MECHANICAL POLISHING METHOD AND CHEMICAL MECHANICAL POLISHING DEVICE
    Publication number: 20090170323
    Abstract: A chemical mechanical polishing method including a step of forming a plurality of interlayer insulating films so as to coat a plurality of projecting patterns, at least one of the plurality of projecting patterns being formed on each of a plurality of substrates, whereby the plurality of projection patterns have different area ratios R with respect to the corresponding substrates, and performing a flattening process on the interlayer insulating films before linear approximation; a step of obtaining a linear approximation formula R=aT+b expressing a relationship between the area ratio R and a polishing time T, where R1, R2, R3, . . . , Rx represent the area ratio R of each of the projecting patterns with respect to the corresponding substrates, and T1, T2, T3, . . .
    Type: Application
    Filed: December 19, 2008
    Publication date: July 2, 2009
    Inventors: MASANORI MIYATA, Taro Usami, Koichi Sogawa, Kenji Nishihara, Tadao Uehara, Shisyo Chin, Hiroaki Teratani, Akinori Suzuki, Yuuichi Kohno, Tetsuya Okada, Tohru Haruki