Patents by Inventor Yuuichi OSHINO

Yuuichi OSHINO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11522075
    Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: December 6, 2022
    Assignee: SANKEN ELECTRIC CO., LTD.
    Inventor: Yuuichi Oshino
  • Publication number: 20210151590
    Abstract: A semiconductor device according to one or more embodiments may include a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type with a higher impurity concentration than an impurity concentration of the first semiconductor region, the second semiconductor region being provided on a first principal surface of the first semiconductor region, a third semiconductor region of a second conductivity type provided on an upper surface of the second semiconductor region, the third semiconductor region being doped with an impurity in accordance with an impurity concentration profile including peaks along a film thickness direction, a fourth semiconductor region of the first conductivity type provided on an upper surface of the third semiconductor region.
    Type: Application
    Filed: January 28, 2021
    Publication date: May 20, 2021
    Applicant: SANKEN ELECTRIC CO., LTD.
    Inventor: Yuuichi OSHINO
  • Patent number: 9613951
    Abstract: According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: April 4, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Yuuichi Oshino
  • Patent number: 9324815
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: April 26, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
  • Patent number: 9324816
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: April 26, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoko Matsudai, Yuuichi Oshino, Bungo Tanaka
  • Publication number: 20160064536
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a first gate electrode, a first region, and a second region. The third semiconductor region is provided on the second semiconductor region. The fourth semiconductor region is provided on the third semiconductor region. The first region is provided in the second semiconductor region. The first region is positioned between the first semiconductor region and the third semiconductor region. The second region is provided in the second semiconductor region. The second region is positioned between the first region and the gate electrode. A carrier density of the first conductivity type in the second region is higher than a carrier density of the first conductivity type in the first region.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 3, 2016
    Inventors: Bungo Tanaka, Tomoko Matsudai, Yuuichi Oshino
  • Publication number: 20160035840
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor layer, a second semiconductor layer provided in a portion on the first semiconductor layer, a first insulating layer provided on the first semiconductor layer on a terminal region side of the second semiconductor layer, a third semiconductor layer provided on the first semiconductor layer on the terminal region side of the first insulating layer, a second insulating layer provided on the first semiconductor layer on the terminal region side of the third semiconductor layer, a fourth semiconductor layer provided between the first semiconductor layer and the second insulating layer, and a plurality of field plate electrodes provided inside an inter-layer insulating film, the plurality of field plate electrodes having mutually-different distances from the first semiconductor layer.
    Type: Application
    Filed: March 6, 2015
    Publication date: February 4, 2016
    Inventors: Tomoko Matsudai, Yuuichi Oshino, Bungo Tanaka
  • Publication number: 20150380535
    Abstract: According to one embodiment, a semiconductor device includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a fourth semiconductor region, a fifth semiconductor region, and a gate electrode. The length in a first direction of a portion of the gate electrode opposing the third semiconductor region being longer than a length in the first direction of a portion of the gate electrode opposing the fifth semiconductor region. An impurity concentration of the second conductivity type of the fourth semiconductor region is higher than an impurity concentration of the second conductivity type of an intermediate portion in the third semiconductor region. At least a part of the intermediate portion is arranged with a part of the first insulating region in the third direction. At least a part of the fifth semiconductor region is not arranged with the first insulating region in the third direction.
    Type: Application
    Filed: March 5, 2015
    Publication date: December 31, 2015
    Inventors: Yuuichi Oshino, Tsuneo Ogura
  • Publication number: 20150236104
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 20, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO
  • Patent number: 9054066
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: June 9, 2015
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo Ogura, Tomoko Matsudai, Yuuichi Oshino, Yoshiko Ikeda, Kazutoshi Nakamura, Ryohei Gejo
  • Publication number: 20140284658
    Abstract: According to one embodiment, a semiconductor device includes a first and second electrode, a first, second, third and fourth semiconductor region, and a first intermediate metal film. The first region is provided above the first electrode and has a first impurity concentration. The second region is provided above the first region and has a second impurity concentration lower than the first impurity concentration. The third region is provided above the second region and has a third impurity concentration. The fourth region is provided above the second region and has a fourth impurity concentration lower than the third impurity concentration. The second electrode is provided above the third region and the fourth region and is in ohmic contact with the third region. The intermediate metal film is provided between the second electrode and the fourth region. The intermediate metal film forms Schottky junction with the fourth region.
    Type: Application
    Filed: March 6, 2014
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tsuneo Ogura, Yuuichi Oshino
  • Publication number: 20140084336
    Abstract: According to one embodiment, an IGBT region includes: a collector layer of a first conductivity type, a drift layer of a second conductivity type, a body layer of the first conductivity type, and a second electrode extending to the drift layer and the body layer via a first insulating film in a stacking direction of a first electrode and the collector layer. A diode region includes: a cathode layer of the second conductivity type, the drift layer, an anode layer of the first conductivity type, and a conductive layer extending to the drift layer and the anode layer via a second insulating film in the stacking direction. The second electrode and the conductive layer are separated from one another at a predetermined distance.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 27, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoko Matsudai, Tadashi Matsuda, Kazutoshi Nakamura, Yuuichi Oshino
  • Publication number: 20140061875
    Abstract: According one embodiment, a semiconductor device includes: a first electrode; a second electrode; a first semiconductor layer provided between the first electrode and the second electrode and being in contact with the first electrode; a second semiconductor layer including a first part and a second part, and the second part being contact with the first electrode, and the second semiconductor layer having an effective impurity concentration lower than an effective impurity concentration in the first semiconductor layer; a third semiconductor layer provided between the second semiconductor layer and the second electrode, and having an effective impurity concentration lower than an effective impurity concentration in the second semiconductor layer; and a fourth semiconductor layer provided between the third semiconductor layer and the second electrode, and being in contact with the second electrode.
    Type: Application
    Filed: August 29, 2013
    Publication date: March 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsuneo OGURA, Tomoko MATSUDAI, Yuuichi OSHINO, Yoshiko IKEDA, Kazutoshi NAKAMURA, Ryohei GEJO