Patents by Inventor Yuuji Hanaoka

Yuuji Hanaoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8032793
    Abstract: In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 4, 2011
    Assignee: Fujitsu Limited
    Inventors: Terumasa Haneda, Yuichi Ogawa, Yuuji Hanaoka, Toshiyuki Yoshida, Hidenori Takahashi
  • Patent number: 7640374
    Abstract: A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: December 29, 2009
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Tomozaki, Toshiyuki Yoshida, Yuichi Ogawa, Terumasa Haneda, Yuuji Hanaoka
  • Patent number: 7624324
    Abstract: A file control system performing DMA (direct memory access) transfer is provided. The file control system includes file control devices, and each of the file control devices is provided between a host computer and an external storage device. A first file control device among the file control devices checks for errors in the data read from a memory, changes the error detection code added to the read data from a first error detection code to a second error detection code, changes at least a part of the data when an error is detected, and executes DMA-transfer of the data, which is changed or is not changed, to a second file control device of the transfer destination.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: November 24, 2009
    Assignee: Fujitsu Limited
    Inventors: Yuuji Hanaoka, Toshiyuki Yoshida, Yuichi Ogawa, Terumasa Haneda, Kazunori Masuyama
  • Publication number: 20060190772
    Abstract: A file control system of the present invention is a file control system performing DMA transfer and comprising a plurality of file control devices, each of which is provided between a host computer and an external storage device, a first file control device among the plurality of file control devices, checks the consistency between the data read from a memory and the first error detection code given in advance to the data, changes the error detection code added to the read data from the first error detection code to a second error detection code, when the inconsistency is detected by the check, changes at least a part of the data comprising the second error detection code and the data associated with the second error detection code, and executes DMA-transfer of the data which is changed or is not changed to a second file control device of the transfer destination.
    Type: Application
    Filed: September 29, 2005
    Publication date: August 24, 2006
    Applicant: Fujitsu Limited
    Inventors: Yuuji Hanaoka, Toshiyuki Yoshida, Yuichi Ogawa, Terumasa Haneda, Kazunori Masuyama
  • Publication number: 20060161694
    Abstract: A DMA apparatus which reads data corresponding to a descriptor from memory, and a dividing unit in a descriptor management device divides one descriptor into a plurality of sub-descriptors. A plurality of DMA controllers produce a plurality of reading requests for reading data corresponding to the plurality of sub-descriptors from the memory. A memory controller reads the corresponding data from the memory according to the plurality of reading requests.
    Type: Application
    Filed: August 4, 2005
    Publication date: July 20, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Tomozaki, Toshiyuki Yoshida, Yuichi Ogawa, Terumasa Haneda, Yuuji Hanaoka
  • Publication number: 20060159115
    Abstract: In a method of controlling an information processing system in which an information processing device is connected to each of a plurality of input/output ports provided in a routing device and having a first property or a second property, for conducting data transmission among the information processing devices via the routing device, a step of causing all of the information processing devices to halt data transmission, a step of resetting properties and identification information of the input/output ports with the second properties other than the input/output port with the first property which cannot be used, in the routing device, and a step of causing the information processing devices to restart the data transmission after the reset of the identification information are executed.
    Type: Application
    Filed: September 29, 2005
    Publication date: July 20, 2006
    Applicant: Fujitsu Limited
    Inventors: Terumasa Haneda, Yuichi Ogawa, Yuuji Hanaoka, Toshiyuki Yoshida, Hidenori Takahashi