Abstract: An information processing apparatus includes a processor, and a memory connected to the processor, that stores a piece of identification information allocated to a physical partition in the information processing apparatus. The processor executes a process including collecting pieces of the identification information that are stored by other information processing apparatuses included in an information processing system. The process includes notifying an operating system of the pieces of the identification information collected at the collecting.

Abstract: In a system including a plurality of CPU units having a cache memory of different capacity each other and a system controller that connects to the plurality of CPUs and controls cache synchronization, the system controller includes a cache synchronization unit which monitors an address contention between a preceding request and a subsequent request and a setting unit which sets different monitoring range of the contention between the preceding request and the subsequent request for each capacity of the cache memory in each of the CPU units.

Abstract: A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.

Abstract: An information processing apparatus includes a processor, and a memory connected to the processor, that stores a piece of identification information allocated to a physical partition in the information processing apparatus. The processor executes a process including collecting pieces of the identification information that are stored by other information processing apparatuses included in an information processing system. The process includes notifying an operating system of the pieces of the identification information collected at the collecting.

Abstract: When an uncorrectable error (UE) occurs in data read out from a second tag memory corresponding to a first tag memory of an arithmetic processing unit, a system controller issues a notification of WAY information of the second tag memory in which the UE has occurred to the arithmetic processing unit. The arithmetic processing unit degenerates a WAY of the corresponding first tag memory based on the received WAY information and issues a notification of completion of the degeneration process to the system controller. The system controller degenerates the WAY of the second tag memory in which the UE has occurred and re-issues a request relating to the UE after a notification that the degeneration process of the first tag memory is completed is received from the arithmetic processing unit.

Abstract: A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.

Abstract: A method of setting transfer rate for information processing apparatus having a plurality of processing apparatus including a processor outputting data and connected by one or a plurality of data transfer apparatuses for transferring the data outputted from the processor, the method includes obtaining a dividing information indicating a manner of dividing the information processing apparatus into a plurality of partitions including at least one of the plurality of processing apparatuses, and setting a transfer rate of each partition for broadcasting data to all of the processors included in the plurality of processing apparatuses in each partition based on the obtained dividing information.

Abstract: A storage apparatus includes: a plurality of storage sections each of which corresponds to each of a plurality of addresses; a read pointer register that outputs a read pointer indicating an address of a storage section from which data is read; a write pointer register that outputs a write pointer indicating an address of a storage section to which data is written; a control circuit that receives first clock signals of a first frequency and second clock signals of a second frequency that is different from the first frequency, determines selection signals indicating either the first clock signals or the second clock signals on the basis of the read pointer or the write pointer for each of the plurality of storage sections, and outputs the selection signals; and selection circuits selects signals indicated by the selection signals, and outputs the selected signals.

Abstract: In a frame transfer method and apparatus, a data entry into a content addressable memory is set to enable, and upon receipt of a transfer frame addressed to a first apparatus from a line bus, header information of the frame is entered into the content addressable memory based on the setting that the entry is enabled. The frame prepared based on header information entered into a content addressable memory of a second apparatus and transmitted by the second apparatus can be used, and the frame is discarded when it is not addressed to the first apparatus. Furthermore, normal frame processing is performed when the entry is not enabled by the setting.

Abstract: In a communication apparatus performing communication using IP packets, a diagnostic frame terminator terminates a series of latest status information of diagnosed devices recorded in a diagnostic frame every time the diagnostic frame sequentially passes through a series of diagnosed devices connected in cascade; a content addressable memory preliminarily stores therein as a single entry a series of normal status information in which each status information of the series of diagnosed devices in a normal state is arranged in an order of connection of the diagnosed devices, and generates an abnormality notification when the terminated series of latest status information does not hit the entry; a status information storage stores the terminated series of latest status information; and a CPU acquires, upon receipt of the abnormality notification, the terminated series of the latest status information from the status information storage to be outputted.

Abstract: In a frame transfer method and apparatus, a data entry into a content addressable memory is set to enable, and upon receipt of a transfer frame addressed to a first apparatus from a line bus, header information of the frame is entered into the content addressable memory based on the setting that the entry is enabled. The frame prepared based on header information entered into a content addressable memory of a second apparatus and transmitted by the second apparatus can be used, and the frame is discarded when it is not addressed to the first apparatus. Furthermore, normal frame processing is performed when the entry is not enabled by the setting.

Abstract: In a communication apparatus performing communication using IP packets, a diagnostic frame terminator terminates a series of latest status information of diagnosed devices recorded in a diagnostic frame every time the diagnostic frame sequentially passes through a series of diagnosed devices connected in cascade; a content addressable memory preliminarily stores therein as a single entry a series of normal status information in which each status information of the series of diagnosed devices in a normal state is arranged in an order of connection of the diagnosed devices, and generates an abnormality notification when the terminated series of latest status information does not hit the entry; a status information storage stores the terminated series of latest status information; and a CPU acquires, upon receipt of the abnormality notification, the terminated series of the latest status information from the status information storage to be outputted.

Abstract: A memory socket, particularly a detachable memory card (DIMM), in which equal-length wiring can be obtained in a wiring design, is provided. A memory socket for mounting a detachable memory card on a circuit board is comprised of a first memory socket in which a first memory card is inserted, with a surface facing upward and a second memory socket in which a second memory card is inserted, with the other surface facing upward. The first memory socket and the second memory socket are arranged adjacent each other on said circuit board. The first and second memory cards are inserted from the outside of the first and second memory sockets, in opposite directions.

Abstract: A memory socket, particularly a detachable memory card (DIMM), in which equal-length wiring can be obtained in a wiring design, is provided. A memory socket for mounting a detachable memory card on a circuit board is comprised of a first memory socket in which a first memory card is inserted, with a surface facing upward and a second memory socket in which a second memory card is inserted, with the other surface facing upward. The first memory socket and the second memory socket are arranged adjacent each other on said circuit board. The first and second memory cards are inserted from the outside of the first and second memory sockets, in opposite directions.