Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.

Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Abstract: A semiconductor device according to an embodiment of the present disclosure includes: a first substrate including a first junction portion; and a second substrate including a second junction portion. The second junction portion is joined to the first junction portion. The first substrate further includes a first multilayer wiring layer in which one surface of a first wiring line faces a first insulating layer and another surface opposed to the one surface is in contact with a second insulating layer. The first multilayer wiring layer is electrically coupled to the first junction portion via the first insulating layer. The first wiring line is formed closest to a junction surface with the second substrate. The second insulating layer has a lower relative dielectric constant than a relative dielectric constant of the first insulating layer.

Abstract: An imaging device comprises a first chip that includes a first semiconductor substrate including a photoelectric conversion region. The first chip includes a first insulating layer including a first multilayer wiring electrically connected to the photoelectric conversion region. The first multilayer wiring includes a first vertical signal line (VSL1) to output a first pixel signal, and a first wiring. The imaging device includes a second chip including a second semiconductor substrate including a logic circuit. The second chip includes a second insulating layer including a second multilayer wiring electrically connected to the logic circuit. The second multilayer wiring includes a second wiring. The first chip and the second chip are bonded to one another, and, in a plan view, the first wiring and the second wiring overlap with at least a portion of the first vertical signal line (VSL1).

Abstract: To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.