Abstract: A system and method is disclosed for fast secure destruction or erasure of data in a non-volatile memory. The method may include identifying a fast erase condition, such as an unauthorized access attempt, and then applying a fast erase process to a predetermined number of blocks of the non-volatile memory. The fast erase process may be implemented by applying an erase voltage for less than a full duration needed to place the blocks in a full erase state, but sufficient to make any data in those blocks unreadable. The system may include a non-volatile memory having a plurality of blocks and a controller configured to sequentially apply the erase voltage to a predetermined portion of the blocks for less than a time needed to fully erase those blocks such that the controller may rapidly make data unreadable without taking the full time to completely erase those blocks.

Abstract: A storage device and method for detecting and handling burst operations are provided. In one embodiment, a method for operating a storage device in burst mode is provided. The storage device senses a change in behavior of a host in communication with the storage device, determines whether the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode by comparing the sensed change in behavior with prior changes in behavior that triggered prior burst modes in the storage device, and in response to determining that the sensed change in behavior of the host is indicative of the host's need for the storage device to operate in burst mode, operates the storage device in burst mode. Other embodiments are provided.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: A system and method for data tag sharing is disclosed. A host system may provide a storage system with information that identifies a set of logical addresses as pointing to data that is cold, which may mean that the data has not been written to within a threshold time period, such as a year. The storage system may process the data stored at physical locations corresponding to the set of logical addresses as cold data based on receipt of the information from the host system.

Abstract: In a flash memory two or more pages in a plane are read in rapid succession by maintaining global word line voltages throughout multiple page reads, and by simultaneously transitioning the old selected word line from a discrimination voltage to a read voltage and transitioning the new selected word line from the read voltage to a discrimination voltage.

Abstract: Certain aspects of a method and system for coalescing task completions may include coalescing a plurality of completions per connection associated with an I/O request. An event may be communicated to a global event queue, and an entry may be posted to the global event queue for a particular connection based on the coalesced plurality of completions. At least one central processing unit (CPU) may be interrupted based on the coalesced plurality of completions.

Abstract: Certain aspects of a method and system for host software concurrent processing of a network connection using multiple central processing units (CPUs) may be disclosed. Exemplary aspects of the method may include a network system comprising a plurality of processors and a NIC. After completion of one or more received I/O requests, a plurality of completions may be distributed among two or more of the plurality of CPUs. The plurality of CPUs may be enabled to handle processing for one or more network connections and each network connection may be associated with a plurality of completion queues. Each CPU may be associated with at least one global event queue.