Patents by Inventor Yuval Neeman

Yuval Neeman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11778558
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive, from a base station, one or more downlink grants scheduling one or more corresponding downlink transmissions from the base station to the UE. In some examples, the UE may enter a state of sleep prior to receiving the one or more downlink transmissions. In such examples, the UE may wake up from the state of sleep at a first time that is at least a threshold period of time before a second time corresponding to a beginning of the one or more downlink transmissions. After waking up from the state of sleep, the UE may activate a notch filter and use the activated notch filter to filter a spur generated at the UE. The UE may receive the one or more downlink transmissions with improved reliability based on activating the notch filter.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: October 3, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Igor Gutman, Christian Pietsch, Oren Matsrafi, Ronen Greenberger, Yossi Waldman, Jong Hyeon Park, Yuval Neeman, Peter Zillmann
  • Publication number: 20220361101
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may receive, from a base station, one or more downlink grants scheduling one or more corresponding downlink transmissions from the base station to the UE. In some examples, the UE may enter a state of sleep prior to receiving the one or more downlink transmissions. In such examples, the UE may wake up from the state of sleep at a first time that is at least a threshold period of time before a second time corresponding to a beginning of the one or more downlink transmissions. After waking up from the state of sleep, the UE may activate a notch filter and use the activated notch filter to filter a spur generated at the UE. The UE may receive the one or more downlink transmissions with improved reliability based on activating the notch filter.
    Type: Application
    Filed: May 5, 2021
    Publication date: November 10, 2022
    Inventors: Igor Gutman, Christian Pietsch, Oren Matsrafi, Ronen Greenberger, Yossi Waldman, Jong Hyeon Park, Yuval Neeman, Peter Zillmann
  • Publication number: 20210211981
    Abstract: Methods, systems, and devices for wireless communications are described. A user equipment (UE) may identify conditions associated with one or more physical channels, for example, a set of resources with which the UE may be configured to communicate with a base station. The UE may determine whether to enable a reduced power mode based on the conditions satisfying certain criteria, for example, the set of resources corresponding allocated for particular transmissions. The UE may identify that the conditions satisfy corresponding criteria, and the UE may determine to enable the reduced power mode. The UE may accordingly modify operations one or more components of a receive chain of the UE. The UE may determine to disable the reduced power mode based on the conditions failing to satisfy the criteria, and the UE may modify operations of the one or more components of the receive chain accordingly.
    Type: Application
    Filed: January 8, 2020
    Publication date: July 8, 2021
    Inventors: Ronen Greenberger, Igor Gutman, Oren Matsrafi, Yossi Waldman, Gideon Shlomo Kutz, Christian Pietsch, Shay Landis, Peter Zillmann, Assaf Touboul, Yuval Neeman
  • Patent number: 8924829
    Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: December 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Eliya Babitsky, Noam Zach
  • Patent number: 8638244
    Abstract: An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.
    Type: Grant
    Filed: August 31, 2009
    Date of Patent: January 28, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Eliya Babitsky, Yosef Kazaz
  • Patent number: 8627022
    Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect, coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information elemen
    Type: Grant
    Filed: January 21, 2008
    Date of Patent: January 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Ron Bercovich, Guy Drory, Dror Gilad, Aviel Livay, Yonatan Naor
  • Patent number: 8595584
    Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: November 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
  • Patent number: 8413033
    Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: April 2, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Guy Drory, Ron Bercovich, Aviel Livay, Ilia Moskovich, Yuval Neeman
  • Publication number: 20120147988
    Abstract: An encoding module comprises an inverse interleaving module arranged to: determine an initial location index within an interleaving matrix for a data bit; and perform bit reverse ordering (BRO) on a column index value for the initial location index for the data bit to obtain a BRO column index value for the data bit. The inverse interleaving module is further arranged to calculate a number of valid interleaving matrix addresses preceding a location index for the data bit following bit reverse ordering; and determine a position of the data bit within the interleaved data stream based on the calculated number of valid addresses.
    Type: Application
    Filed: August 31, 2009
    Publication date: June 14, 2012
    Inventors: Yuval Neeman, Eliya Babitsky, Yosef Kazaz
  • Publication number: 20120151295
    Abstract: A method for turbo-encoding a block of data including: receiving data bits of the block of data; masking irrelevant data bits by a masking unit, wherein irrelevant data bits are data bits that regardless of their value do not affect a final state of an interleaved convolutional encoder of a turbo encoder; calculating a last state of the interleaved convolutional encoder based on relevant data bits provided by the masking unit; wherein the calculating of the last state of the interleaved convolutional encoder is initialized before receiving the entire block of data; finding an initial state of the interleaved convolutional encoder based on the last state of the interleaved convolutional encoder; wherein the initial state of the interleaved convolutional encoder equals a final state of the interleaved convolutional encoder; initializing the interleaved convolutional encoder to the initial state; and turbo-encoding the interleaved data bits by the interleaved convolutional encoder.
    Type: Application
    Filed: August 31, 2009
    Publication date: June 14, 2012
    Inventors: Yuval Neeman, Eliya Babitsky, Noam Zach
  • Patent number: 8200733
    Abstract: A method and a device having interleaving capabilities, the device comprises a first interleaver; the first interleaver comprises a first register, a second register, a first adder and a second adder; wherein the first register is coupled to the first adder and to the second adder; wherein the second register is coupled to the second adder; wherein the first adder is adapted to add a current first register value to a first coefficient to provide a next first register value that is stored at the first register; wherein the second adder is adapted to add a current first register value to a second coefficient, to a third coefficient and to a current second register value to provide an interleaved output value.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: June 12, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Ron Berkovich, Guy Drory, Gilad Dror, Aviel Livay, Yonatan Naor
  • Patent number: 8171384
    Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: May 1, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Guy Drory, Ron Bercovich, Yosef Kazaz, Aviel Livay, Yonatan Naor, Yuval Neeman
  • Publication number: 20110060963
    Abstract: A semiconductor device comprising processing logic. The processing logic is arranged to configure interleaver logic to re-order data symbols of a data stream according to a quadrature permutation polynomial function. The processing logic is further arranged to: divide a cyclic group of values defined by the QPP function into a set of subgroups, the set of subgroups being capable of being defined by a set of linear functions; derive inverse functions for the set of linear functions defining the subgroups; and configure the interleaver logic to load the data symbols of the data stream into a buffer at locations within the buffer corresponding to a cyclic group of values representative of the inverse function for the QPP function based on the inverse functions of the set of linear functions defining the subgroups.
    Type: Application
    Filed: May 19, 2008
    Publication date: March 10, 2011
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
  • Publication number: 20110019781
    Abstract: A method for calculating backward state metrics of a trellis, the method includes: performing a radix-K calculation of backward state matrices of multiple states of at least one time instance of a trellis; and performing a radix-J calculation of backward state matrices of multiple states of at least one other time instance of the trellis; wherein K differs from J.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Inventors: Guy Drory, Ron Bercovich, Aviel Livay, Ilia Moskovich, Yuval Neeman
  • Publication number: 20100287343
    Abstract: A parallel access system including: a group of processing entities that comprises N processing entities; wherein N is a positive integer that exceeds one; a group of memory banks that stores K information elements; wherein the group of memory banks comprises N pairs of single access memory banks; each pair of memory banks comprises an even memory bank and an odd memory bank; wherein each pair of memory banks stores sub-set of K/N information elements; wherein an even memory bank of each pair of memory banks stores even address information elements of a certain sub-set of K/N information elements and an odd memory bank of each pair of memory banks stores odd address information elements of the certain sub-set of K/N information elements; wherein K/N is an even positive integer; and a non-blocking interconnect coupled to the group of processing entities and to the group of memory banks; wherein during each fetch cycle each processing entity of the group of processing entities fetches a first information element
    Type: Application
    Filed: January 21, 2008
    Publication date: November 11, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Yuval Neeman, Ron Bercovich, Guy Drory, Dror Gilad, Aviel Livay, Yonatan Naor
  • Patent number: 7760114
    Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: July 20, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yuval Neeman, Guy Drory, Aviel Livay, Inbar Schori
  • Publication number: 20100111291
    Abstract: A method for generating an interleaved output during a decoding of a data block, the method includes: (i) selecting, in response to a row indicator, a row register and a multiplication factor to provide a selected row register and a selected multiplication factor; wherein the selected multiplication factor is responsive to a size of the data block; (ii) multiplying a value stored in the selected row register by the selected multiplication factor to provide an intermediate result; (iii) performing a modulo P operation on the intermediate result to provide a permutated result; wherein the permutated result and the value stored in the selected row register are adjacent elements of the same permutation; wherein P is responsive to a size of the data block; (iv) writing the permutated result to the selected row register; and (v) outputting a data block element that is selected in response to the permutated result.
    Type: Application
    Filed: October 30, 2008
    Publication date: May 6, 2010
    Inventors: Yuval NEEMAN, Guy DRORY, Aviel LIVAY, Inbar SCHORI
  • Publication number: 20090327834
    Abstract: A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric of multiple windows of a channel data block for a current iteration of the turbo decoding process by at least one corresponding state metric that was calculated during a previous iteration of the turbo decoding process; and (ii) calculating in parallel, at least forward state metrics and backward state metrics of the multiple windows, during the current iteration.
    Type: Application
    Filed: June 27, 2008
    Publication date: December 31, 2009
    Inventors: Guy Drory, Ron Bercovich, Yosef Kazaz, Aviel Livay, Yonatan Naor, Yuval Neeman
  • Patent number: 6081898
    Abstract: A software system unifies directory services with the file system. Directory service entries and other files are all stored in a common logical format, such as an object format. The unification of files with directory service entries allows a common set of tools to operate on both such entities and allows a common name space to be utilized. Security measures are taken so as to prevent unauthorized access to the directory service entries.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: June 27, 2000
    Assignee: Microsoft Corporation
    Inventors: Arnold Miller, Yuval Neeman, Aaron M. Contorer, Pradyumna K. Misra, Michael R. C. Seaman, Darryl E. Rubin
  • Patent number: 5842214
    Abstract: A distributed file system uses objects to model the behavior of components of the distributed file system. Each object has an associated logical path name and physical address. An aggregation of all the logical path names comprises a distributed name space which can be logically partitioned into domains. Each domain includes a domain folder object which maps logical path names of objects in the domain containing the domain folder object, into addresses in the distributed system where the objects are stored. The addresses of the objects are used to access the objects in order to retrieve information from the distributed system.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: November 24, 1998
    Assignee: Microsoft Corporation
    Inventors: Alan Whitney, Yuval Neeman, Sudheer Koneru, Milan Shah, Peter J. Cook, Arnold S. Miller