Patents by Inventor Yu-Wei Liao

Yu-Wei Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240194523
    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes an interconnect dielectric layer over a substrate. An interconnect via is within the interconnect dielectric layer, and an interconnect wire is over the interconnect via and within the interconnect dielectric layer. A protective layer surrounds the interconnect via. The interconnect via vertically extends through the protective layer to below a bottom of the protective layer. The protective layer continuously extends from along an outer sidewall of the interconnect via to along an outer sidewall of the interconnect wire in a first cross-sectional view.
    Type: Application
    Filed: February 21, 2024
    Publication date: June 13, 2024
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
  • Publication number: 20240162088
    Abstract: An integrated circuit device includes an interconnect layer, a memory structure, a third conductive feature, and a fourth conductive feature. The interconnect layer includes a first conductive feature and a second conductive feature. The memory structure is over and in contact with the first conductive feature. The memory structure includes at least a resistance switching element over the first conductive feature. The third conductive feature, including a first conductive line, is over and in contact with the second conductive feature. The fourth conductive feature is over and in contact with the memory structure. The fourth conductive feature includes a second conductive line, a top surface of the first conductive line is substantially level with a top surface of the second conductive line, and a bottom surface of the first conductive line is lower than a bottommost portion of a bottom surface of the second conductive line.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hsia-Wei CHEN, Fu-Ting SUNG, Yu-Wen LIAO, Wen-Ting CHU, Fa-Shen JIANG, Tzu-Hsuan YEH
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11980041
    Abstract: Various embodiments of the present application are directed towards an integrated chip comprising memory cells separated by a void-free dielectric structure. In some embodiments, a pair of memory cell structures is formed on a via dielectric layer, where the memory cell structures are separated by an inter-cell area. An inter-cell filler layer is formed covering the memory cell structures and the via dielectric layer, and further filling the inter-cell area. The inter-cell filler layer is recessed until a top surface of the inter-cell filler layer is below a top surface of the pair of memory cell structures and the inter-cell area is partially cleared. An interconnect dielectric layer is formed covering the memory cell structures and the inter-cell filler layer, and further filling a cleared portion of the inter-cell area.
    Type: Grant
    Filed: June 1, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsia-Wei Chen, Wen-Ting Chu, Yu-Wen Liao
  • Publication number: 20240145380
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 2, 2024
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
  • Publication number: 20240136420
    Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.
    Type: Application
    Filed: December 1, 2022
    Publication date: April 25, 2024
    Applicant: AUO Corporation
    Inventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
  • Publication number: 20240126001
    Abstract: A switchable backlight module is disclosed. The switchable backlight module includes two light source modules arranged parallelly with respect to a plane. Each of the light source modules includes a turning film and a LGP. The LGP is of an edge-lit type arranged parallelly under the turning film. A light ray enters the LGP from a light incident side of the LGP, exits the LGP from a light emergent surface of the LGP, enters the turning film, and exits the turning film from a surface of the turning film away from the LGP. The light incident side of the LGP of one of the light source modules is perpendicular to the light incident side of the LGP of the other light source module. The switchable backlight module is in an anti-peeping mode having a narrow viewing angle when only an upper one of the light source modules emits light.
    Type: Application
    Filed: July 19, 2023
    Publication date: April 18, 2024
    Inventors: YU-HUAN CHIU, CHIEN-WEI LIAO, YEN-LUNG CHEN
  • Publication number: 20240114810
    Abstract: A semiconductor structure includes: an etch-stop dielectric layer overlying a substrate and including a first opening therethrough; a silicon oxide plate overlying the etch-stop dielectric layer and including a second opening therethrough; a first conductive structure including a first electrode and extending through the second opening and the first opening; a memory film contacting a top surface of the first conductive structure and including a material that provides at least two resistive states having different electrical resistivity; and a second conductive structure including a second electrode and contacting a top surface of the memory film.
    Type: Application
    Filed: April 20, 2023
    Publication date: April 4, 2024
    Inventors: Fu-Ting Sung, Jhih-Bin Chen, Hung-Shu Huang, Hong Ming Liu, Hsia-Wei Chen, Yu-Wen Liao, Wen-Ting Chu
  • Publication number: 20240109803
    Abstract: The present invention provides a flexible glass and manufacturing method thereof. The flexible glass includes a first straight part and a second straight part on two opposite ends thereof, a recess formed between the first straight part and the second straight part, and a pre-bent curve connection part disposed corresponding to the recess. The first straight part and the second straight part are not arranged on the same plane. The flexible glass has a first lateral side and a second lateral side, and the recess sinks from the first lateral side toward the second lateral side. Therefore, the flexible glass is provided with a greater bendability.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: CHENFENG OPTRONICS CORPORATION
    Inventors: CHING-FANG WONG, YU-WEI LIU, WEI-LUN ZENG, KUAN-HUA LIAO
  • Patent number: 11942364
    Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai, Wei-Hao Liao
  • Publication number: 20240088022
    Abstract: Some embodiments relate to an integrated chip including a plurality of conductive structures over a substrate. A first dielectric layer is disposed laterally between the conductive structures. A spacer structure is disposed between the first dielectric layer and the plurality of conductive structures. An etch stop layer overlies the plurality of conductive structures. The etch stop layer is disposed on upper surfaces of the spacer structure and the first dielectric layer.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 14, 2024
    Inventors: Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien, Wei-Hao Liao
  • Patent number: 11923293
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Wei-Hao Liao, Yu-Teng Dai
  • Publication number: 20210153778
    Abstract: Smart apparel for monitoring athletics and associated systems and methods are disclosed. An example apparatus includes a data interface to access first motion data and second motion data generated by the smart apparel, the first motion data associated with a first joint on a body and the second motion data associated with a second joint on the body; a motion data fuser to fuse the first motion data and the second motion data; an analytics determiner to process the fused first and second motion data to identify a progression of a motion based activity; and a display organizer to generate a graphical display representing the progression of the motion based activity.
    Type: Application
    Filed: August 10, 2017
    Publication date: May 27, 2021
    Inventors: Anupama Gupta, Timothy Hansen, Lili Jiang, Todd Johnson, Gary Kwan, Wenlong Li, Yu-Wei Liao, Bhaveshkumar Makwana, Alok Mishra, Kisang Pak, Mary Smiley, Sun Hee Wee, Johnny Yip
  • Patent number: 10497604
    Abstract: A transportation stage for transporting a photomask is provided. The transportation stage includes a vacuum source and a supporting plate. The supporting plate has a number of passages connected to the vacuum source. The transportation stage further includes a membrane positioned on the supporting plate. A number of through holes are formed on a middle region of the membrane and communicating with the passages. The transportation stage also includes an acoustic wave transducer positioned on the membrane and is configured generate an acoustic wave along the membrane.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: December 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Ching Lee, Yu-Piao Fang, Yu-Wei Liao
  • Publication number: 20180287583
    Abstract: A transportation stage for transporting a photomask is provided. The transportation stage includes a vacuum source and a supporting plate. The supporting plate has a number of passages connected to the vacuum source. The transportation stage further includes a membrane positioned on the supporting plate. A number of through holes are formed on a middle region of the membrane and communicating with the passages. The transportation stage also includes an acoustic wave transducer positioned on the membrane and is configured generate an acoustic wave along the membrane.
    Type: Application
    Filed: May 5, 2017
    Publication date: October 4, 2018
    Inventors: Yu-Ching LEE, Yu-Piao FANG, Yu-Wei LIAO
  • Patent number: 8723897
    Abstract: An exemplary display panel includes a plurality of monochrome pixels, a plurality of data lines and a plurality of control lines. Each monochrome pixel provides a specific color on the display panel. The data lines are electrically coupled to the monochrome pixels for providing the display data. The data lines includes a first data line electrically coupled to a part of the monochrome pixels, and the specific colors provided by the part of the monochrome pixels are of the same color. Besides, each of the control lines is electrically coupled to a part of the monochrome pixels for controlling the part of the monochrome pixels electrically coupled thereto whether to receive the display data from the data lines.
    Type: Grant
    Filed: August 26, 2011
    Date of Patent: May 13, 2014
    Assignee: AU Optronics Corp.
    Inventors: Hsiang-Yuan Cheng, Shih-Hsun Lo, Shan-Fu Yuan, Chen-Lun Chiu, Yu-Wei Liao, Chia-Yang Cheng
  • Patent number: 8581829
    Abstract: Exemplary backlight driving method and display device are provided. The display device includes a light source array. The light source array includes a first group of light-emitting rows and a second group of light-emitting rows. The backlight driving method includes the steps of: firstly, receiving a gate driving frequency of the display device; subsequently, generating a backlight driving frequency according to the gate driving frequency; and afterwards, sequentially providing a first row driving voltage to the first group of light-emitting rows in a first time period and sequentially providing a second row driving voltage to the second group of light-emitting rows in a second time period, according to the backlight driving frequency. The first time period and the second time period have different phases from each other, and the gate driving frequency is different from the backlight driving frequency.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: November 12, 2013
    Assignee: AU Optronics Corp.
    Inventors: Hsiang-Yuan Cheng, Shih-Hsun Lo, Chen-Lun Chiu, Shan-Fu Yuan, Yu-Wei Liao
  • Publication number: 20120162278
    Abstract: An exemplary display panel includes a plurality of monochrome pixels, a plurality of data lines and a plurality of control lines. Each monochrome pixel provides a specific color on the display panel. The data lines are electrically coupled to the monochrome pixels for providing the display data. The data lines includes a first data line electrically coupled to a part of the monochrome pixels, and the specific colors provided by the part of the monochrome pixels are of the same color. Besides, each of the control lines is electrically coupled to a part of the monochrome pixels for controlling the part of the monochrome pixels electrically coupled thereto whether to receive the display data from the data lines.
    Type: Application
    Filed: August 26, 2011
    Publication date: June 28, 2012
    Applicant: AU OPTRONICS CORP.
    Inventors: Hsiang-Yuan Cheng, Shih-Hsun Lo, Shan-Fu Yuan, Chen-Lun Chiu, Yu-Wei Liao, Chia-Yang Cheng
  • Publication number: 20110273367
    Abstract: Exemplary backlight driving method and display device are provided. The display device includes a light source array. The light source array includes a first group of light-emitting rows and a second group of light-emitting rows. The backlight driving method includes the steps of: firstly, receiving a gate driving frequency of the display device; subsequently, generating a backlight driving frequency according to the gate driving frequency; and afterwards, sequentially providing a first row driving voltage to the first group of light-emitting rows in a first time period and sequentially providing a second row driving voltage to the second group of light-emitting rows in a second time period, according to the backlight driving frequency. The first time period and the second time period have different phases from each other, and the gate driving frequency is different from the backlight driving frequency.
    Type: Application
    Filed: October 15, 2010
    Publication date: November 10, 2011
    Applicant: AU OPTRONICS CORP.
    Inventors: Hsiang-Yuan Cheng, Shih-Hsun Lo, Chen-Lun Chiu, Shan-Fu Yuan, Yu-Wei Liao
  • Patent number: D1018441
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: March 19, 2024
    Assignee: Cheng Shin Rubber Industrial Co., Ltd.
    Inventors: Yu Chieh Chen, Yu Shiuan Lin, Chia Hao Chang, Ku Wei Liao, Yi Ru Chen