Abstract: A Decision Feedback Equalizer (DFE) with programmable taps includes a summer configured to receive a DFE input signal. Delay elements are coupled to the summer. The delay elements are connected in series. Each delay element provides a respective delayed signal of an input signal to the delay element. A weight generator is configured to provide tap weights. The DFE is configured to multiply each tap weight to the respective delayed signal from the respective delay element to provide tap outputs. Each tap output is selectively enabled to be added to the summer or disabled based on a first comparison of a first threshold value and each impulse response or each tap weight corresponding to the respective tap output, where the impulse response is the DFE input signal in response to a pulse signal transmitted through a channel.

Abstract: A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: A voltage regulator circuit comprises an amplifier having an inverting input and a non-inverting input. The amplifier is configured to generate a control signal based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the amplifier. The voltage regulator circuit also comprises an output node, a first power node, a second power node, and a driver that generates a driving current flowing toward the output node in response to the control signal. The driver is coupled between the first power node and the output node. A first transistor having a gate is coupled between the output node and the second power node. A bias circuit outside the amplifier supplies a bias signal to the gate of the first transistor, which is configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

Abstract: A method of operating a voltage regulator circuit includes generating a control signal by an amplifier of the voltage regulator circuit. The control signal is generated based on a reference signal at an inverting input of the amplifier and a feedback signal at a non-inverting input of the amplifier. A driving current flowing toward an output node of the voltage regulator circuit is generated by a driver responsive to the control signal, and the driver is coupled between a first power node and the output node. The feedback signal is generated responsive to a voltage level at the output node. A transistor, coupled between the output node and a second power node, is caused to operate in saturation mode during a period while the voltage regulator circuit is operating.

Abstract: A clock data recovery circuit (CDR) extracts bit data values from a serial bit stream without reference to a transmitter clock. A controllable oscillator produces a regenerated clock signal controlled to match the frequency and phase of transitions between bits and the serial data is sampled at an optimal phase. A phase detector generates early-or-late indication bits for clock versus data transition times, which are accumulated and applied to a second order feedback control with two distinct feedback paths for frequency and phase, combined for correcting the controllable oscillator, selecting a sub-phase and/or determining an optimal phase at which the bit stream data values are sampled. The second order filter is operated at distinct rates such that the phase correction has a latency as short as one clock cycle and the frequency correction latency occurs over plural cycles.

Abstract: A method of making a level shifter includes coupling a driver stage between an input end and an output end, the driver stage comprising a first transistor and a second transistor. An inverter having an input is coupled with the input end. A third transistor having a gate end is coupled with an output of the inverter, the third transistor having a terminal coupled to a pumped voltage (VPP). Additionally, the method includes coupling a fourth transistor with the output end, the fourth transistor having a terminal coupled to the pumped voltage. A fifth transistor is coupled with the input end, the fifth transistor having a terminal coupled to the third and fourth transistors. A sixth transistor is coupled with the input end, the sixth transistor having a terminal.

Abstract: An inductor-capacitor phase locked loop (LCPLL) includes an inductor-capacitor voltage controlled oscillator (LCVCO) that provides an output frequency. A calibration circuit includes two comparators and provides a coarse tune signal to the LCVCO. The two comparators respectively compare the loop filter signal with a first reference voltage and a second reference voltage that is higher than the first reference voltage to supply a first and second comparator output, respectively. The calibration circuit is capable of adjusting the coarse tune signal continuously in voltage values and adjusts the coarse tune signal based on the two comparator outputs. A loop filter provides a loop filter signal to the calibration circuit and a fine tune signal to the LCVCO. A coarse tune frequency range is greater than a fine tune frequency range.

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition. The circuitry comprises at least one pre-driver stage having at least one output node, and the at least one output node of the at least one pre-driver stage is electrically coupled with at least one input node of a driver stage.

Abstract: A method of sharing inductors for inductive peaking of an amplifier includes calculating a single stage inductance of a single stage for inductive peaking in order to have a stable impulse response. The method further includes determining a number of stages for shared inductance for inductive peaking. The method further includes sharing at least two inductors having the shared inductance among the determined number of stages for inductive peaking.

Abstract: A phase interpolator for a CDR circuit produces an output clock having level transitions between the level transitions on two input clocks. The input clocks drive cross-coupled differential amplifiers with an output that can be varied in phase by variable current throttling or steering, according to an input control value. The differential amplifiers produce an output signal with a transition spanning a time between the start of a transition on the leading input clock up to the end of the transition on the lagging input clock. The output clock is linear so long as the transitions on the two input clocks overlap. Active integrators each having an amplifier with a series resistance and capacitive feedback path are coupled to each input to the cross-coupled differential amplifiers, which enhances overlap of the input clock rise times and improves the linearity of the interpolated output signal.

Abstract: A circuit has a first circuit module including a first resistor and first and second transistors coupled in parallel with the first resistor. The first resistor and the first and second transistors are coupled together at a first node. An equivalent resistance across the first circuit module increases as a voltage of the first node is increased from a first voltage to a second voltage, and the equivalent resistance across the first circuit module decreases as the voltage of the first node is increased from the second voltage to a third voltage.

Abstract: A level shifter includes an input end being capable of receiving an input voltage signal. The input voltage signal includes a first state transition from a first voltage state to a second voltage state. An output end can output an output voltage signal having a second state transition from a third voltage state to the second voltage state corresponding to the first state transition of the input voltage signal. A driver stage is coupled between the input end and the output end. The driver stage includes a first transistor and a second transistor. Substantially immediately from a time corresponding to about a mean of voltage levels of the first voltage state and the second voltage state, the second voltage state is substantially free from being applied to a gate of the first transistor so as to substantially turn off the first transistor.

Abstract: An input/output (I/O) circuit includes an electrostatic discharge (ESD) protection circuit electrically coupled with an output node of the I/O circuit. At least one inductor and at least one loading are electrically coupled in a series fashion and between the output node of the I/O circuit and a power line. A circuitry is electrically coupled with a node between the at least one inductor and the at least one loading. The circuitry is operable to increase a current flowing through the at least one inductor during a signal transition.

Abstract: A circuit includes a summation circuit for receiving an input data signal and a feedback signal including a previous data bit. The summation circuit is configured to output a conditioned input data signal to a clock and data recovery circuit. A first flip-flop is coupled to an output of the summation circuit and is configured to receive a first set of bits of the conditioned input data signal and a first clock signal having a frequency that is less than a frequency at which the input data signal is received by the first summation circuit. A second flip-flop is coupled to the output of the summation circuit and is configured to receive a second set of bits of the conditioned input data signal and a second clock signal having a frequency that is less than the frequency at which the input data signal is received by the first summation circuit.

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.

Abstract: A method of sharing inductors for inductive peaking of an amplifier having at least two stages includes calculating a single stage inductance of a single stage of the at least two stages for inductive peaking in order to have a stable impulse response. A shared inductance is calculated for inductive peaking by dividing the single stage inductance by a number of stages of the at least two stages. At least two inductors having the shared inductance are shared among the at least two stages for inductive peaking.