Patents by Inventor Yuya MAEDA
Yuya MAEDA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240158659Abstract: The present invention provides a pre-coating agent capable of, without containing a polyvalent metal salt, preventing or reducing mottling and bleeding to improve the print image quality and preventing or reducing strike-through of an ink composition for inkjet recording during printing using the ink composition for inkjet recording, as well as being capable of preventing or reducing peeling and a decrease in hardness of an overcoat layer in the post-process (formation of the overcoat layer). Provided is a pre-coating agent for forming a precoat layer to receive an ink composition for inkjet recording, the pre-coating agent containing inorganic particles, an amine salt of an organic acid, a resin emulsion, and water, the inorganic particles having a particle size of 1 ?m to 10 ?m, the pre-coating agent being free from a polyvalent metal salt.Type: ApplicationFiled: March 22, 2022Publication date: May 16, 2024Inventors: Hirohito MAEDA, Hiroyuki KONISHI, Yuya WATANABE, Ryohei MIYAKE
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Publication number: 20240155084Abstract: A building entrance device (10B) of an intercom device includes a touch operable aerial display (100) for displaying an aerial image (G1, G2) toward a visitor (W1, W2), and a control unit (110). The touch operable aerial display (100) includes: a display device (101) for emitting light; an optical member (102) for reflecting and transmitting light so as to form the aerial image (G1, G2) in a predetermined space; and a detection unit (103) for detecting an operation input of the visitor (W1, W2) to the aerial image (G1, G2). The control unit (110) changes at least one from among a display position, a display angle of the aerial images (G1, G2), and a display mode of a call operation acceptance unit included in the aerial images (G1, G2).Type: ApplicationFiled: March 23, 2022Publication date: May 9, 2024Inventors: Kazuyuki MORITA, Yuya HINO, Hirokazu KUSUNOKI, Takayuki GOTO, Yu SHIMIZU, Ryoji MAEDA
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Patent number: 11965508Abstract: A scroll compressor includes a housing, a rotary shaft rotatably supported by the housing, a fixed scroll accommodated in the housing and fixed to the housing, an orbiting scroll that orbits as the rotary shaft rotates, a compression chamber defined between the fixed scroll and the orbiting scroll, a discharge chamber, and an oil passage. A refrigerant taken in from the outside is compressed in the compression chamber. The refrigerant compressed in the compression chamber is discharged into the discharge chamber. An outer peripheral space connected to the compression chamber is defined between the outer peripheral surface of the fixed scroll and the inner peripheral surface of the housing. Oil separated from the refrigerant discharged into the discharge chamber is guided to the outer peripheral space through the oil passage.Type: GrantFiled: March 15, 2023Date of Patent: April 23, 2024Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Takumi Maeda, Yuya Hattori
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Publication number: 20240030250Abstract: Provided is a solid-state imaging device capable of acquiring an image with higher image quality. It includes a plurality of pixel units including on-chip lenses, color filters, and photoelectric conversion units. The plurality of pixel units includes a first pixel unit (e.g., a pixel unit of an imaging pixel) and a second pixel unit (e.g., a pixel unit of a phase-difference detection pixel), the first pixel unit including an on-chip lens of a predetermined size, the second pixel unit including an on-chip lens of a size larger than the predetermined size, the first pixel unit including first pixel units, the second pixel unit including second pixel units. A height of an inter-CF light-shielding portion surrounding the respective color filters of the second pixel units is larger than a height of an inter-CF light-shielding portion between the color filters of the first pixel units.Type: ApplicationFiled: August 2, 2021Publication date: January 25, 2024Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Kazuya FURUMOTO, Yuya MAEDA, Yoshiaki KITANO
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Publication number: 20230299630Abstract: A first molded coil that is one of two molded coils disposed adjacent to each other includes: a first winding part in which a conductor is stacked from a first turn to an n-th turn (n is an integer of 2 or more); and a first terminal part that has a lead part extending from a portion of the first turn of the first winding part in a direction orthogonal to a stacking direction of the conductor in the first winding part, in which the first terminal part is provided at a tip with a first engaging part that is engaged with a second engaging part disposed at a tip of a third terminal part of a second molded coil that is the other molded coil of the two molded coils.Type: ApplicationFiled: May 24, 2021Publication date: September 21, 2023Inventors: YUYA MAEDA, YASUAKI MATSUSHITA, HIROKAZU YAMAUCHI
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Publication number: 20230006496Abstract: A bus bar guide is provided to fix bus bars that connect a plurality of coils disposed in a motor. The bus bar includes a conductor that has a plate shape and has a first surface and a second surface continuous with the first surface. The bus bar guide is configured by annularly arranging a plurality of bus bar guide pieces each including an insulator. Each of the plurality of bus bar guide pieces is provided with a groove that holds the first surface of the bus bar and positions the bus bar.Type: ApplicationFiled: October 20, 2020Publication date: January 5, 2023Inventors: YUYA MAEDA, YASUAKI MATSUSHITA, HIROKAZU YAMAUCHI
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Patent number: 11411452Abstract: A coil is a coil of a conductive wire that has a quadrangular cross section, that is spirally wound and laminated to have a series of turns including first to n-th turns (n is an integer of 3 or more), and that is provided, on at least some of the first to n-th turns in the coil, with deformed portions representing recesses each having a shape different from a shape of another portion of the conductive wire. In each of the first and n-th turns respectively lying at both ends of the series of turns, an outer surface lying on a side opposite to a center of the series of turns extends flush along with a plane intersecting the series of turns.Type: GrantFiled: April 10, 2019Date of Patent: August 9, 2022Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yuya Maeda, Toshiyuki Tamamura, Mitsuoki Hishida, Kiyomi Kawamura
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Publication number: 20220238590Abstract: An imaging device according to embodiments of the present disclosure includes: a first semiconductor substrate provided with a photoelectric conversion element, floating diffusion that temporarily holds a charge output from the photoelectric conversion element, and a transfer transistor that transfers the charge output from the photoelectric conversion element to the floating diffusion; and a second semiconductor substrate provided on the first semiconductor substrate via a first interlayer insulating film and provided with a readout circuit unit that reads out the charge held in the floating diffusion and outputs a pixel signal.Type: ApplicationFiled: June 17, 2020Publication date: July 28, 2022Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATIONInventors: Katsunori HIRAMATSU, Shintaro OKAMOTO, Yoshiaki KITANO, Yuya MAEDA, Shinya SATO
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Publication number: 20210359566Abstract: A stator includes a yoke, teeth connected to the yoke, and coils including plate-shaped conductive wire and mounted on respective teeth. Each coil includes a wound part, a first and second terminals. The wound part is wound around the tooth n turns (n is an integer equal to or greater than 2). The wound part satisfies a relationship represented by Ak<Bk, where Ak is a height of a first section in an axial direction of the tooth, and Bk is a width of a second section in a circumferential direction of the tooth. The first and second sections are sections in k-th turn (k is an integer that satisfies 1?k?n) of the coil. The first section is along an axial end surface of the tooth. The second section extends from an end of the first section along a circumferential end surface of the tooth.Type: ApplicationFiled: September 3, 2019Publication date: November 18, 2021Inventors: Keiichiro NUKADA, Toshiyuki TAMAMURA, Yuya MAEDA
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Patent number: 11077835Abstract: A control apparatus for a vehicle includes: a first road surface friction coefficient calculator; a second road surface friction coefficient calculator; and a braking and driving force controller. The first road surface friction coefficient calculator calculates a first road surface friction coefficient that is a friction coefficient of a road surface in a contact with a wheel. The second road surface friction coefficient calculator calculates a second road surface friction coefficient on a basis of a detection value from a contactless sensor that contactlessly detects a road surface state.Type: GrantFiled: January 7, 2019Date of Patent: August 3, 2021Assignee: SUBARU CORPORATIONInventors: Yuya Maeda, Noeru Sato, Fumiya Sato
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Publication number: 20210021167Abstract: A coil is a coil of a conductive wire that has a quadrangular cross section, that is spirally wound and laminated to have a series of turns including first to n-th turns (n is an integer of 3 or more), and that is provided, on at least some of the first to n-th turns in the coil, with deformed portions representing recesses each having a shape different from a shape of another portion of the conductive wire. In each of the first and n-th turns respectively lying at both ends of the series of turns, an outer surface lying on a side opposite to a center of the series of turns extends flush along with a plane intersecting the series of turns.Type: ApplicationFiled: April 10, 2019Publication date: January 21, 2021Inventors: YUYA MAEDA, TOSHIYUKI TAMAMURA, MITSUOKI HISHIDA, KIYOMI KAWAMURA
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Patent number: 10672788Abstract: A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.Type: GrantFiled: August 30, 2018Date of Patent: June 2, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuya Maeda, Hidenori Miyagawa
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Patent number: 10615170Abstract: A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.Type: GrantFiled: February 26, 2018Date of Patent: April 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Yuya Maeda, Hidenori Miyagawa
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Publication number: 20190299948Abstract: A control apparatus for a vehicle includes: a first road surface friction coefficient calculator; a second road surface friction coefficient calculator; and a braking and driving force controller. The first road surface friction coefficient calculator calculates a first road surface friction coefficient that is a friction coefficient of a road surface in a contact with a wheel. The second road surface friction coefficient calculator calculates a second road surface friction coefficient on a basis of a detection value from a contactless sensor that contactlessly detects a road surface state.Type: ApplicationFiled: January 7, 2019Publication date: October 3, 2019Applicant: SUBARU CORPORATIONInventors: Yuya MAEDA, Noeru SATO, Fumiya SATO
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Publication number: 20190296039Abstract: A semiconductor memory device includes conductive layers and insulation layers alternately stacked along a first direction. A core member extends through the insulation layers and conductive layers. A semiconductor layer on an outer periphery of the core member has a first region facing a conductive layer of the stack and a second region adjacent to the first region and facing an insulation layer. The first region has a first thickness and a first impurity concentration. The second region has a second thickness that is greater than the first thickness and a second impurity concentration that is different from the first impurity concentration. A charge accumulation film is between the semiconductor layer and the conductive layer in a second direction crossing the first direction.Type: ApplicationFiled: August 30, 2018Publication date: September 26, 2019Inventors: Yuya MAEDA, Hidenori MIYAGAWA
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Publication number: 20190088673Abstract: A semiconductor memory device, including: a substrate; a plurality of first conductive layers arranged in a first direction intersecting a surface of the substrate; a channel semiconductor layer extending in the first direction and including a first portion facing the plurality of the first conductive layers and a second portion further from the substrate than the first portion; a memory layer arranged between the first portion of the channel semiconductor layer and the plurality of the first conductive layers and including a memory part capable of storing data; and a first semiconductor layer connected to the second portion of the channel semiconductor layer, the first semiconductor layer including crystalline semiconductor containing a first impurity, and the channel semiconductor layer including a crystal grain having a crystal grain size larger than a thickness thereof.Type: ApplicationFiled: February 26, 2018Publication date: March 21, 2019Applicant: TOSHIBA MEMORY CORPORATIONInventors: Yuya MAEDA, Hidenori MIYAGAWA
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Patent number: 9871060Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer. The third semiconductor is provided between the first semiconductor layer and the second semiconductor layer. A first transistor includes a first gate electrode and a first amorphous semiconductor layer. The first gate electrode and the first amorphous semiconductor layer overlap in a first direction. The first direction is from the first semiconductor layer toward the second semiconductor layer. The first gate electrode is provided between the second semiconductor layer and the first amorphous semiconductor layer.Type: GrantFiled: February 9, 2016Date of Patent: January 16, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Nobuyoshi Saito, Tomio Ono, Shigeya Kimura, Jumpei Tajima, Kentaro Miura, Shintaro Nakano, Yuya Maeda
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Patent number: 9837549Abstract: According to one embodiment, an oxide semiconductor includes indium, gallium, and silicon. A concentration of the silicon in the oxide semiconductor is not less than 7 atomic percent and not more than 11 atomic percent.Type: GrantFiled: September 16, 2016Date of Patent: December 5, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Keiji Ikeda, Shintaro Nakano, Yuya Maeda, Tomomasa Ueda, Kentaro Miura, Nobuyoshi Saito, Tsutomu Tezuka
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Patent number: 9780220Abstract: According to one embodiment, a semiconductor device includes an oxide semiconductor transistor. The oxide semiconductor transistor includes a semiconductor layer including an oxide semiconductor, the semiconductor layer including a source region and a source electrode. The source electrode includes a source conductive layer including copper, a first tantalum-containing region provided between the source conductive layer and the source region, the first tantalum-containing region including tantalum, a first low nitrogen composition region provided between the first tantalum-containing region and the source region, the first low nitrogen composition region including Ta1?x1Nx1 (0<x1<0.5), and a first high nitrogen composition region provided between the first low nitrogen composition region and the source region, the first high nitrogen composition region including Ta1?x2Nx2 (0.5?x2<1).Type: GrantFiled: August 30, 2016Date of Patent: October 3, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Yuya Maeda, Shintaro Nakano, Nobuyoshi Saito, Hajime Yamaguchi
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Publication number: 20170141131Abstract: According to one embodiment, a semiconductor device includes a substrate, a semiconductor layer, a source electrode, a drain electrode, first insulating portion and second insulating portions. The semiconductor layer includes an oxide and is separated from the substrate in a first direction. The source electrode is electrically connected to the semiconductor layer. The drain electrode is electrically connected to the semiconductor layer and is arranged with the source electrode in a second direction crossing the first direction. The first insulating portion is provided between the substrate and the semiconductor layer. The semiconductor layer is provided between the first and second insulating portions. The first insulating portion includes a first silicon nitride layer, and a first aluminum oxide layer stacked with the first silicon nitride layer. The second insulating portion includes a second aluminum oxide layer, and a second silicon nitride layer stacked with the second aluminum oxide layer.Type: ApplicationFiled: January 27, 2017Publication date: May 18, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Shintaro NAKANO, Kentaro MIURA, Yuya MAEDA