Patents by Inventor Yuya Shigenobu

Yuya Shigenobu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11882269
    Abstract: An image encoding method includes, using an image as input, determining a first mode suited to encode the image in accordance with a first processing procedure; using the image as input, determining a second mode suited to encode the image in accordance with a second processing procedure; selecting one of first mode and the second mode as a final mode; encoding the image, using the final mode; and calculating a cost of using the second mode to encode the image. The second processing procedure is implemented by a reconfigurable circuit. In the selecting, the first mode is selected when the cost calculated in the calculating is higher than a first predetermined value, and the second mode is selected when the cost is lower than or equal to the first predetermined value.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: January 23, 2024
    Assignee: SOCIONEXT INC.
    Inventors: Yuya Shigenobu, Masao Kitagawa
  • Publication number: 20210235070
    Abstract: An image encoding method includes, using an image as input, determining a first mode suited to encode the image in accordance with a first processing procedure; using the image as input, determining a second mode suited to encode the image in accordance with a second processing procedure; selecting one of first mode and the second mode as a final mode; encoding the image, using the final mode; and calculating a cost of using the second mode to encode the image. The second processing procedure is implemented by a reconfigurable circuit. In the selecting, the first mode is selected when the cost calculated in the calculating is higher than a first predetermined value, and the second mode is selected when the cost is lower than or equal to the first predetermined value.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Yuya SHIGENOBU, Masao KITAGAWA
  • Patent number: 9532044
    Abstract: An arithmetic decoding device includes a calculating unit that calculates candidates for split information using probability information, the split information indicating a boundary between a first value range and a second value range in range information, the probability information indicating whether a next item of binary data takes the first or second value, and the range information indicating a possible range of positional information obtained from a stream; a selecting unit that selects the split information corresponding to the range information from among the candidates; and a generating unit that generates the binary data according to which range of the range information divided at the split information includes the positional information and generates a next piece of the range information and a next piece of the positional information using the generated binary data. A process of the calculating unit and that of the generating unit are pipelined.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 27, 2016
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Yuya Shigenobu
  • Publication number: 20140205010
    Abstract: An arithmetic decoding device includes a calculating unit that calculates candidates for split information using probability information, the split information indicating a boundary between a first value range and a second value range in range information, the probability information indicating whether a next item of binary data takes the first or second value, and the range information indicating a possible range of positional information obtained from a stream; a selecting unit that selects the split information corresponding to the range information from among the candidates; and a generating unit that generates the binary data according to which range of the range information divided at the split information includes the positional information and generates a next piece of the range information and a next piece of the positional information using the generated binary data. A process of the calculating unit and that of the generating unit are pipelined.
    Type: Application
    Filed: March 25, 2014
    Publication date: July 24, 2014
    Applicant: PANASONIC CORPORATION
    Inventor: Yuya SHIGENOBU
  • Patent number: 8228214
    Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Yuya Shigenobu, Motokazu Ozawa, Nobuo Higaki, Takeshi Furuta, Takahiro Kageyama, Masaki Minami
  • Publication number: 20110280318
    Abstract: A multiview video decoding apparatus which sufficiently suppresses artifact in a decoded image even when an error occurs in the to-be-decoded image. It decodes a video stream including first coded video information of a first viewpoint and second coded video information of a second viewpoint, and includes: a decoding unit which decodes the video stream; and an error detecting unit which detects an error in the video stream; and an error concealing unit which conceals the error and includes (i) a decoding control unit which, when the error is in first coded image information in the first coded video information, causes said decoding unit to decode second coded image information included in the second coded video information and to be decoded after the first coded image information and (ii) a concealment processing unit which conceals the detected error, using decoded image information generated by decoding the second coded image information.
    Type: Application
    Filed: July 27, 2011
    Publication date: November 17, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Takeshi YADO, Yuya SHIGENOBU
  • Publication number: 20110268195
    Abstract: In a multiview video decoding device conforming to H.264/AVC, the amount of calculation in a reordering process on a reference picture list is reduced. This is achieved as follows. A view index selector extracts only an entry or entries whose view IDs correspond to an inter-view reference flag which is 1 from a view ID list which defines an association between view indices and view IDs, stores the view indices of the extracted entry or entries as search targets into a view index storing section, and searches for and selects a view index which is equal to a given variable picViewIdxLX (X is 0 or 1). A view ID selector stores the view IDs of the extracted entry or entries as a reference picture list, and selects a view ID based on an address of an entry hit in the view index storing section.
    Type: Application
    Filed: July 12, 2011
    Publication date: November 3, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Yuya SHIGENOBU
  • Publication number: 20100289674
    Abstract: A variable-length code decoding apparatus that decodes a bitstream includes: a storage unit that stores a variable-length code table; a bitstream cutout unit that outputs a bit string of a fixed length; a reference unit that outputs decoded data and a code length with reference to the storage unit; a determination unit that determines whether a bit string of the fixed length is accumulated; a determination unit that determines whether a bit string of a length that is shorter than the fixed length is accumulated; and a selection unit that selects one of the determination results from the determination units. The bitstream cutout unit sets a starting bit based on the selected determination result, and the selection unit switches the selection of the determination results from the determination units.
    Type: Application
    Filed: July 27, 2010
    Publication date: November 18, 2010
    Applicant: PANASONIC CORPORATION
    Inventors: Yuya SHIGENOBU, Motokazu OZAWA, Nobuo HIGAKI, Takeshi FURUTA, Takahiro KAGEYAMA, Masaki MINAMI
  • Patent number: 7728745
    Abstract: A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the
    Type: Grant
    Filed: April 23, 2008
    Date of Patent: June 1, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuya Shigenobu, Yoshiyuki Wada, Satoshi Yamaguchi, Kozo Kimura, Takeshi Furuta
  • Publication number: 20080266147
    Abstract: A variable length code decoding apparatus according to the present invention includes: an extracting unit which extracts a bit string from a beginning of a bit stream; a first storage unit for storing a plurality of code words in which one piece of data has been coded, and decoded data and code lengths respectively corresponding to the code words; a second storage unit for storing a plurality of code words in which two or more pieces of data have been coded, and decoded data and code lengths respectively corresponding to the code words; a first judging unit which judges whether one of the code words stored in the first storage unit is included in the extracted bit string, and, when judged as being included, outputs the decoded data and the code length of the code word; and a second judging unit which judges whether a code word stored in the second storage unit is included in the extracted bit string, and when judged as being included, outputs the decoded data and the code length of the code word, wherein the
    Type: Application
    Filed: April 23, 2008
    Publication date: October 30, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Yuya SHIGENOBU, Yoshiyuki WADA, Satoshi YAMAGUCHI, Kozo KIMURA, Takeshi FURUTA