Patents by Inventor Yu-Yuan Wang

Yu-Yuan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12002699
    Abstract: A wafer pod transfer assembly includes a wafer pod port to receive a wafer pod, a transfer axle coupled to the wafer pod port, a shaft receiver, a shaft coupled to the transfer axle and to the shaft receiver, a pin through the shaft receiver and through the shaft, wherein the pin comprises a first end and a second end, opposite the first end, and a pin buckle including a first loop and a second loop. The pin buckle is coupled to the pin, the first loop encircles the first end of the pin, and the second loop encircles the second end of the pin.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chih-Wei Chou, Sheng-Yuan Lin, Yuan-Hsin Chi, Yin-Tun Chou, Hung-Chih Wang, Yu-Chi Liu
  • Publication number: 20240162094
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, a conductive feature on the substrate, and an electrical connection structure on the conductive feature. The electrical connection includes a first grain made of a first metal material, and a first inhibition layer made of a second metal layer that is different than the first metal material. The first inhibition layer extends vertically along a first side of a grain boundary of the first grain and laterally along a bottom of the grain boundary of the first grain.
    Type: Application
    Filed: January 5, 2024
    Publication date: May 16, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shih-Chuan CHIU, Jia-Chuan YOU, Chia-Hao CHANG, Chun-Yuan CHEN, Tien-Lu LIN, Yu-Ming LIN, Chih-Hao WANG
  • Publication number: 20240137599
    Abstract: A terminal, comprising one or a plurality of processors, wherein the one or plurality of processors execute a machine-readable instruction to perform: receiving an object in a live streaming; displaying the object on the terminal; detecting a keyword in the object corresponding to a function in the live streaming; and triggering the function in response to an operation on the object. The present disclosure may allow the streamers to generate or amend an object such as stickers on the live streaming room in a more flexible manner. At the same time, the viewer may perform an operation on the object to realize a corresponding function in a more convenient manner. Therefore, the interaction among streamers and viewers may be increased, and the user experience may also be enhanced.
    Type: Application
    Filed: July 2, 2023
    Publication date: April 25, 2024
    Inventors: Yu-Cheng FAN, Sz-Chi HUANG, Chih-Yuan WANG
  • Publication number: 20240125995
    Abstract: An image sensor includes a group of sensor units and a color filter layer disposed within the group of sensor units. The image sensor further includes a dielectric structure and a plurality of polarization splitters disposed corresponding to the color filter layer. Each of the plurality of polarization splitters has a first meta element extending in a first direction from top view and a second meta element extending in a second direction from top view. The second direction is perpendicular to the first direction.
    Type: Application
    Filed: October 12, 2022
    Publication date: April 18, 2024
    Inventors: Chun-Yuan WANG, Yu-Chi CHANG, Po-Hsiang WANG
  • Patent number: 11961768
    Abstract: A method includes forming a first transistor, which includes forming a first gate dielectric layer over a first channel region in a substrate and forming a first work-function layer over the first gate dielectric layer, wherein forming the first work-function layer includes depositing a work-function material using first process conditions to form the work-function material having a first proportion of different crystalline orientations and forming a second transistor, which includes forming a second gate dielectric layer over a second channel region in the substrate and forming a second work-function layer over the second gate dielectric layer, wherein forming the second work-function layer includes depositing the work-function material using second process conditions to form the work-function material having a second proportion of different crystalline orientations.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen Chiu, Da-Yuan Lee, Hsien-Ming Lee, Kai-Cyuan Yang, Yu-Sheng Wang, Chih-Hsiang Fan, Kun-Wa Kuok
  • Publication number: 20240105546
    Abstract: A module device on a first substrate includes a power module, a housing, a pair of locking structures. The housing covers the power module. The locking structures are installed on a pair of opposite sides of the housing, and the locking structure includes a main body, a locking ring, a pair of ribs and anchoring portions. The locking ring extends from a side toward an inner side of the main body, and is a double-ring structure, which includes an inner and an outer ring. A first side of the outer ring is connected to the main body, a second side of the outer ring is connected to the inner ring. The ribs extend along a normal direction of the top surface of the main body. The anchoring portions are disposed at the end of the ribs, and an extending direction is perpendicular to an extending direction of the rib.
    Type: Application
    Filed: January 10, 2023
    Publication date: March 28, 2024
    Applicant: Industrial Technology Research Institute
    Inventors: Ji-Yuan Syu, Yuan-Cheng Huang, Yu-Chih Wang
  • Patent number: 8206683
    Abstract: A method for synthesizing the all-silica zeolite beta with small crystal size is disclosed. This method comprises the steps of: (a) forming a reaction mixture comprising (1) a source of silicon dioxide (SiO2), (2) a source of fluoride ions (F?), (3) a source of tetraethylammonium cations (TEA+), and (4) water (H2O), at predetermined mole ratios of the source of silicon dioxide, the source of fluoride ions, the source of tetraethylammonium cations, and water; (b) crystallizing the reaction mixture; and (c) recovering the crystalline material formed, wherein the pH of the mixture before crystallization has a value of 6 to 9, and the pH of the mixture after crystallization has a value of 6 to 8. This improved method gives a fast and efficient way of synthesis of all-silica zeolite beta with an average crystal size of less than 5 ?m.
    Type: Grant
    Filed: June 11, 2009
    Date of Patent: June 26, 2012
    Assignee: Formosan Union Chemical Corp.
    Inventors: Yu-Yuan Wang, Chien-Hsun Tsai, Chi-Hsing Tsai
  • Publication number: 20100254894
    Abstract: A method for synthesizing the all-silica zeolite beta with small crystal size is disclosed. This method comprises the steps of: (a) forming a reaction mixture comprising (1) a source of silicon dioxide (SiO2), (2) a source of fluoride ions (F?), (3) a source of tetraethylammonium cations (TEA+), and (4) water (H2O), at predetermined mole ratios of the source of silicon dioxide, the source of fluoride ions, the source of tetraethylammonium cations, and water; (b) crystallizing the reaction mixture; and (c) recovering the crystalline material formed, wherein the pH of the mixture before crystallization has a value of 6 to 9, and the pH of the mixture after crystallization has a value of 6 to 8. This improved method gives a fast and efficient way of synthesis of all-silica zeolite beta with an average crystal size of less than 5 ?m.
    Type: Application
    Filed: June 11, 2009
    Publication date: October 7, 2010
    Inventors: Yu-Yuan Wang, Chien-Hsun Tsai, Chi-Hsing Tsai