Abstract: In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a predetermined program. Responsive to the mode judgment signal, a monitoring signal is generated indicative of an attempt by the CPU to execute the predetermined program during the debugging preparation. Furthermore, a transfer of an instruction code corresponding to the predetermined program is controlled so that the CPU is prevented from executing the predetermined program during the debugging preparation, responsive to the monitoring signal. Alternatively, in the debugging circuit and the method, instead of controlling the transfer of the instruction code responsive to the monitoring signal, another instruction code may be transferred to the CPU, responsive to the mode judgment signal. The another instruction code prevents the CPU from executing the predetermined program during the debugging preparation.

Abstract: A bus configuration circuit includes a first group having a first master module, a first slave module and a first bus module group; a second master module and a second slave module disposed outside the first group and connected thereto by a second bus module group; and a third slave module disposed outside the first group. A first control signal is output from the first bus module group indicative of whether an access destination of the first master module is the first slave module. A second control signal is output from the first slave module indicative of the accessed status of the first slave module. The third slave module consequently outputs a third control signal responsive to the first and second control signals.

Abstract: A semiconductor integrated circuit has an SDRAM and a group of elements, whose power consumption is controlled (referred to as “power-controlled block”). The power-controlled block includes a CPU and a memory control circuit. A power control circuit outputs a power-down signal to an output-fixing circuit when a power-saving mode setting command is supplied from the CPU. A control signal for commanding self-refresh operation is generated from the output-fixing circuit to the SDRAM. The power control circuit thereafter stops the supply of power to the entire power-controlled block in response to a power control signal. When a restart signal is provided, the power control circuit starts the supply of power to the power-controlled block. A power-saving mode release command is then generated from the CPU to the power control circuit, and the power-down signal is stopped. Thereupon, the output-fixing circuit provides a control signal generated from the memory control circuit directly to the SDRAM.

Abstract: In a debugging circuit and a controlling method of the debugging circuit, a mode judgment signal is generated which indicates that a central processing unit (CPU) is preparing to debug a predetermined program. Responsive to the mode judgment signal, a monitoring signal is generated indicative of an attempt by the CPU to execute the predetermined program during the debugging preparation. Furthermore, a transfer of an instruction code corresponding to the predetermined program is controlled so that the CPU is prevented from executing the predetermined program during the debugging preparation, responsive to the monitoring signal. Alternatively, in the debugging circuit and the method, instead of controlling the transfer of the instruction code responsive to the monitoring signal, another instruction code may be transferred to the CPU, responsive to the mode judgment signal. The another instruction code prevents the CPU from executing the predetermined program during the debugging preparation.

Abstract: The present invention provides a bus configuration circuit capable of normally operating even where signals lines extending from a master module provided outside a PLATFORM to a slave module provided within the PLATFORM are eliminated upon its design using IP (Intellectual Property).