Patents by Inventor Yuzuru Ohji
Yuzuru Ohji has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6927439Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.Type: GrantFiled: August 23, 2004Date of Patent: August 9, 2005Assignee: Hitachi, Ltd.Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
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Patent number: 6881597Abstract: Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 ?m or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 ?m to 0.8 ?m to the first electrode pad.Type: GrantFiled: January 22, 2002Date of Patent: April 19, 2005Assignee: Renesas Technology Corp.Inventors: Kyoichiro Asayama, Yasuhiro Mitsui, Fumiko Arakawa, Shiro Kamohara, Yuzuru Ohji
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Publication number: 20050024811Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.Type: ApplicationFiled: August 23, 2004Publication date: February 3, 2005Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
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Patent number: 6781172Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.Type: GrantFiled: March 8, 2001Date of Patent: August 24, 2004Assignee: Hitachi, Ltd.Inventors: Hiroshi Moriya, Tomio Iwasaki, Hiroyuki Ohta, Shinpei Iijima, Isamu Asano, Yuzuru Ohji, Yoshitaka Nakamura
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Patent number: 6756262Abstract: Conduction reliability between a capacitor upper electrode and a plug connected to an upper layer wire is kept high to prevent connection defects and to reduce the resistance of the capacitor upper electrode. In a capacitor of a DRAM comprising a lower electrode 45 made of ruthenium, a capacitor insulating film 50 made of BST and an upper electrode 49, the upper electrode 49 has a laminate structure comprising a ruthenium film 47 formed on the side of the capacitor insulating film 50 and a tungsten film 48 formed over the former.Type: GrantFiled: November 9, 2000Date of Patent: June 29, 2004Assignee: Hitachi, Ltd.Inventors: Yoshitaka Nakamura, Isamu Asano, Satoru Yamada, Tsugio Takahashi, Yuzuru Ohji, Masayoshi Hirasawa, Takashi Yunogami, Tomonori Sekiguchi
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Patent number: 6720603Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.Type: GrantFiled: December 18, 2002Date of Patent: April 13, 2004Assignee: Hitachi, Ltd.Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
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Patent number: 6717202Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.Type: GrantFiled: October 17, 2002Date of Patent: April 6, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
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Patent number: 6627497Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.Type: GrantFiled: June 5, 2002Date of Patent: September 30, 2003Assignee: Hitachi, Ltd.Inventors: Naruhiko Nakanishi, Nobuyoshi Kobayashi, Yuzuru Ohji, Sinpei Iijima, Yasuhiro Sugawara, Misuzu Kanai
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Patent number: 6583463Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.Type: GrantFiled: October 14, 1998Date of Patent: June 24, 2003Assignee: Hitachi, Ltd.Inventors: Naruhiko Nakanishi, Nobuyoshi Kobayashi, Yuzuru Ohji, Sinpei Iijima, Yasuhiro Sugawara, Misuzu Kanai
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Publication number: 20030107073Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.Type: ApplicationFiled: December 18, 2002Publication date: June 12, 2003Applicant: Hitachi, Ltd.Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
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Patent number: 6576946Abstract: Capacitors are stretched over a plurality of memory cells in the direction of a bit line in order to effectively utilize spaces between adjacent cells. In addition, by creating a cubic structure of each capacitor by adoption of a self-matching technique, the structure can be utilized more effectively. As a result, it is possible to assure a sufficient capacitor capacitance in spite of a limitation imposed by the fabrication technology and obtain an assurance of sufficient space between cells in a shrunk area of a memory cell accompanying high-scale integration and miniaturization of a semiconductor device.Type: GrantFiled: July 20, 1999Date of Patent: June 10, 2003Assignee: Hitachi, Ltd.Inventors: Misuzu Kanai, Yuzuru Ohji, Takuya Fukuda, Shinpei Iijima, Ryouichi Furukawa, Yasuhiro Sugawara, Hideharu Yahata
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Patent number: 6534375Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.Type: GrantFiled: August 8, 2001Date of Patent: March 18, 2003Assignee: Hitachi, Ltd.Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai
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Publication number: 20030038325Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.Type: ApplicationFiled: October 17, 2002Publication date: February 27, 2003Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iijima, Yuzuru Ohji
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Patent number: 6524927Abstract: A first silicon film is so formed as to extend along the inner surface of trenches 52 formed in a silicon oxide film 50, an oxide film is formed on the surface of the first silicon film, and a second amorphous silicon film is further deposited. Heat-treatment is applied to the surface of the second amorphous silicon film for seeding silicon nuclei and for promoting grain growth, and a granular silicon crystal 57 is grown from the second amorphous silicon film. In this way, the resistance of a lower electrode 59 of a capacitance device can be lowered.Type: GrantFiled: September 7, 1999Date of Patent: February 25, 2003Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Yasuhiro Sugawara, Ryouichi Furukawa, Toshio Uemura, Akira Takamatsu, Hirohiko Yamamoto, Tadanori Yoshida, Masayuki Ishizaka, Shinpei Iljima, Yuzuru Ohji
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Publication number: 20030006795Abstract: Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 &mgr;m or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 &mgr;m to 0.8 &mgr;m to the first electrode pad.Type: ApplicationFiled: January 22, 2002Publication date: January 9, 2003Inventors: Kyoichiro Asayama, Yasuhiro Mitsui, Fumiko Arakawa, Shiro Kamohara, Yuzuru Ohji
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Publication number: 20020149044Abstract: A semiconductor integrated circuit device including a memory cell comprising a memory cell selecting MISFET Qs formed on the main surface of a semiconductor substrate 1 and an information storage capacitor C that is connected in series to said memory cell selecting MISFET Qs, and that have a lower electrode 54, a capacitor insulator 58 and an upper electrode 59, wherein the lower electrode 54 is made of a conductive material containing ruthenium dioxide (RuO2) as principle ingredient and the capacitor insulator 58 is made of crystalline tantalum pentoxide. Thus, the capacitance required for the memory cells of a 256 Mbits DRAM or those of a DRAM of a later generation can be secured.Type: ApplicationFiled: June 5, 2002Publication date: October 17, 2002Inventors: Naruhiko Nakanishi, Nobuyoshi Kobayashi, Yuzuru Ohji, Sinpei Iijima, Yasuhiro Sugawara, Misuzu Kanai
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Patent number: 6451665Abstract: Described is a manufacturing method of an integrated circuit which uses a thin film such as platinum or BST as a hard mask upon patterning ruthenium or the like, thereby making it possible to form a device without removing the hard mask. In addition, the invention method makes it possible to interpose a protecting film such as platinum in order to prevent, upon removing a resist used for the patterning of the hard mask, an underlying ruthenium film or the like from being damaged.Type: GrantFiled: December 13, 1999Date of Patent: September 17, 2002Assignee: Hitachi, Ltd.Inventors: Takashi Yunogami, Kazuo Nojiri, Yuzuru Ohji, Sukeyoshi Tsunekawa, Masahiko Hiratani, Yuichi Matsui
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Patent number: 6426255Abstract: After formation of a groove in a silicon oxide film, a Pt film is formed inside of the groove by electroplating using a conductive underlying film, which has been formed in advance below the silicon oxide film, as a cathode electrode. The silicon oxide film is then removed by etching, followed by dry etching of the conductive underlying film with the Pt film as a mask, whereby a lower electrode of a capacitor is formed from the Pt film and the conductive underlying film which has remained below the Pt film.Type: GrantFiled: April 13, 2000Date of Patent: July 30, 2002Assignee: Hitachi, Ltd.Inventors: Isamu Asano, Yoshitaka Nakamura, Yuzuru Ohji, Tatsuyuki Saito, Takashi Yunogami
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Patent number: 6423992Abstract: A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.Type: GrantFiled: May 15, 2001Date of Patent: July 23, 2002Assignee: Hitachi, Ltd.Inventors: Takuya Fukuda, Yuzuru Ohji, Nobuyoshi Kobayashi
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Publication number: 20020022357Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.Type: ApplicationFiled: August 8, 2001Publication date: February 21, 2002Applicant: Hitachi, Ltd.Inventors: Shinpei Iijima, Yuzuru Ohji, Masato Kunitomo, Masahiko Hiratani, Yuichi Matsui, Hiroyuki Ohta, Yukihiro Kumagai