Patents by Inventor Yvette Chung Nga Winton

Yvette Chung Nga Winton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7765677
    Abstract: A method of manufacturing a write pole that prevents P2 pedestal consumption during ion milling removal of coil and pole seed layers. The write head can be constructed by forming a first pole and then forming a magnetic pedestal (P2) over the first pole. A protective layer of, for example, alumina is deposited over a portion of the pedestal in the pole tip region, leaving a portion of the pedestal uncovered in the flare region. A coil seed layer can then be deposited and a coil formed. When the coil seed layer is removed, such as by ion milling, the pole tip region of the pedestal is protected from the ion milling by the protective layer. Similarly, a top pole can be deposited by first depositing an electrically conductive, magnetic seed layer and then plating the top pole. When the top pole seed layer is removed by ion milling, the pole tip region of the pedestal is protected from removal by the protective layer.
    Type: Grant
    Filed: April 18, 2006
    Date of Patent: August 3, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Hamid Balamane, Yvette Chung Nga Winton, Yi Zheng
  • Patent number: 7531907
    Abstract: Both the wafer serial number and slider region location indicia on the wafer are formed on the front surface of the wafer using optical principles, i.e., without using a laser.
    Type: Grant
    Filed: June 13, 2005
    Date of Patent: May 12, 2009
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Unal Murat Guruz, Mary Kathryn Gutberlet, Douglas Johnson Werner, Yvette Chung Nga Winton
  • Patent number: 7251878
    Abstract: A method and apparatus for defining leading edge taper of a write pole tip is disclosed. The fabrication process uses reactive ion etching to fabricate LET with tight control of the placement of LET's edge and to achieve higher angle for providing a higher effective write field at the pole tip while minimizing ATI for high-density perpendicular recording. The placement of a resist's edge is used to define the LET's edge and a CMP process is used to provide a planar surface for the fabrication of the write pole.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: August 7, 2007
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Quang Le, Jui-Lung Li, Yvette Chung Nga Winton, Sue Siyang Zhang, Yi Zheng
  • Patent number: 7129177
    Abstract: During fabrication of a write head via holes are first opened in a gap layer, followed by formation of seed layers instead of the other way around. Moreover a first seed layer is formed, and without the first seed layer being used a second seed layer is formed. The second seed layer (which is the topmost layer) is used in plating to form coils (e.g. of copper) for the write head. After coil formation, the first seed layer is used for plating to form vias (e.g. of NiFe). The two seed layers may be formed in a single operation by using two different targets in a vacuum deposition chamber. Moreover, a single insulation layer is sufficient to insulate and protect all plated elements, regardless of whether they are formed by use of the first seed layer or the second seed layer.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: October 31, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Douglas Kei Tak Tsang, Jorge D. Colonia, Yvette Chung Nga Winton, Michael Ming Hsiang Yang