Abstract: An adaptive current limiter including a conversion network and an amplifier network developing an adaptive current limit signal for use by a switching regulator to limit peak current through an inductor of the switching regulator. The switching regulator develops a pulse control signal for controlling switching of current through the inductor to convert an input voltage to an output voltage. The conversion network provides a limit value by applying a duty cycle of the pulse control signal to a reference value. The amplifier network is configured to develop the adaptive current limit signal based on the limit value. The conversion network may multiply the reference value by the duty cycle to develop the limit value. The amplifier network may include a current source providing a fixed reference current to an amplifier to establish a minimum level of the adaptive current limit signal.

Abstract: A clock driver integrated circuit device and method is provided. The device can include a VTT regulator provided on a single integrated circuit (IC) chip. A first termination at an internal VDD/2 can be coupled to the VTT regulator. A VTT bus can be coupled to the first termination. A plurality of command control inputs can be coupled to the VTT bus. The plurality of command inputs can include A, BA, RAS, CAS, WE, CS, CKE, ODT, PARIN, and the like. A VDD termination can be coupled to a first end of the VTT bus and a ground can be coupled to a second end of the VTT bus. The method can include regulating or removing signal noise from a host controller via the clock driver IC device.

Abstract: An adaptive current limiter including a conversion network and an amplifier network developing an adaptive current limit signal for use by a switching regulator to limit peak current through an inductor of the switching regulator. The switching regulator develops a pulse control signal for controlling switching of current through the inductor to convert an input voltage to an output voltage. The conversion network provides a limit value by applying a duty cycle of the pulse control signal to a reference value. The amplifier network is configured to develop the adaptive current limit signal based on the limit value. The conversion network may multiply the reference value by the duty cycle to develop the limit value. The amplifier network may include a current source providing a fixed reference current to an amplifier to establish a minimum level of the adaptive current limit signal.

Abstract: A filter is configured to receive a filter charging signal and to produce a filter output signal based on the filter charging signal. The filter includes an element array with one or more switched elements which include an element and a switch configured to connect the element to or disconnect the element from the array, thereby altering a time constant of the filter. A comparator is configured to receive the filter output signal and a reference signal corresponding to a value of the filter output when the time constant has a defined value, and to generate a comparator output signal based on a comparison of the filter output signal to the reference signal. A controller is configured to receive the comparator output signal and, based on the comparator output signal, output an array control signal configured to adjust one or more switches of the one or more switched elements of the element array to alter the time constant such that a value of the time constant approaches the defined value.

Abstract: An audio amplifier system includes two amplifiers that are configured to drive loads through either DC or AC coupling. A third amplifier provides an AC ground return when the system is configured in the DC coupled mode, and is disabled when the system is configured in the AC coupled mode. A bypass circuit charges a bypass capacitor to provide a reference voltage level for the amplifiers. A mode detection circuit monitors the reference voltage level and the output of the third amplifier to determine the current operating mode. The third amplifier is disabled when the reference voltage exceeds the output of the third amplifier or when a shutdown condition is activated, such that the third amplifier is protected from short circuit conditions. The charge and discharge times of the bypass capacitor relate to the detected operating mode minimize click and pop in the amplified signals.

Abstract: A single-ended signal is converted to differential signals with a first device that converts an input current of a single-ended input signal to a voltage, a second device coupled to the first device to generate a first output current of a double-ended output signal based on the voltage, and a third device coupled to the first device to generate a second complementary output current of the double-ended output signal based on the voltage. The output currents can be amplified by a gain with respect to the input current, and the gain can be set a relative size of the first device with respect to each of the second and third devices. A fourth device can balance the current gain of the first device and cause the current through the second device and the third device to be equal.

Abstract: An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase blenders (104) output a 0%, 25%, 50%, or 75% interpolation to the adjacent phases. A multiplexer (110) is then used to select which of the phase outputs is used for the write precompensation.

Abstract: A phase mixer is provided which locks a signal to a non-integer multiple of a reference signal. A phase mixer according to the present invention is provided which generates non-integer multiples of a stable reference source, such that an output frequency to an input frequency of the phase mixer has a frequency ratio of f out = f i ⁢   ⁢ n × N N ± M , where N is an integer number of phases of the reference signal and M is an integer less than N and the “+” operation is used when selecting phases in ascending order and the “−” operation is used when selecting phases in descending order.

Abstract: The present invention relates to a conversion circuit that converts a single-ended signal to differential signals. According to an embodiment of the present invention, crosstalk is avoided by insuring that none of the transistors in the conversion circuit are directly connected to ground. By not having a transistor directly connected to ground, ground current is avoided and crosstalk associated with ground current is eliminated.

Abstract: The present invention relates to a conversion circuit that converts a single-ended signal to differential signals. According to an embodiment of the present invention, crosstalk is avoided by insuring that none of the transistors in the conversion circuit are directly connected to ground. By not having a transistor directly connected to ground, ground current is avoided and crosstalk associated with ground current is eliminated.

Abstract: The present invention relates to digital to analog conversion. According to an embodiment of the present invention, an exponential transfer characteristic may be produced by adding a fraction of the output current to a reference current in a recursive equation.

Abstract: The present invention relates to a conversion circuit that converts a single-ended signal to differential signals. According to an embodiment of the present invention, crosstalk is avoided by insuring that none of the transistors in the conversion circuit are directly connected to ground. By not having a transistor directly connected to ground, ground current is avoided and crosstalk associated with ground current is eliminated.

Abstract: The present invention relates to a conversion circuit that converts a single-ended signal to differential signals. According to an embodiment of the present invention, crosstalk is avoided by insuring that none of the transistors in the conversion circuit are directly connected to ground. By not having a transistor directly connected to ground, ground current is avoided and crosstalk associated with ground current is eliminated.

Abstract: The present invention relates to digital to analog conversion. According to an embodiment of the present invention, a logarithmic transfer characteristic may be produced by subtracting a fraction of the output current to a reference current in a recursive equation.

Abstract: A start-up circuit with lower current requirements than a conventional start-up circuit is disclosed. The start-up circuit may achieve lower current requirements by reducing the current of the start-up circuit to approximately zero when the bandgap circuit reaches a predetermined value. For example, the start-up circuit may peak at a current of 3.3 micro Amps in order to ensure that the bandgap circuit reaches the predetermined voltage. Thereafter, the current for the start-up circuit may be reduced to approximately zero once the bandgap circuit no longer requires the start-up circuit.