Patents by Inventor Zachary Matthew Stum
Zachary Matthew Stum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7781312Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.Type: GrantFiled: December 13, 2006Date of Patent: August 24, 2010Assignee: General Electric CompanyInventors: Kevin Sean Matocha, Vinayak Tilak, Stephen Daley Arthur, Zachary Matthew Stum
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Publication number: 20100200931Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.Type: ApplicationFiled: February 10, 2009Publication date: August 12, 2010Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Stephen Daley Arthur, Ramakrishna Rao, Peter Almern Losee, Zachary Matthew Stum
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Patent number: 7691711Abstract: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.Type: GrantFiled: January 31, 2008Date of Patent: April 6, 2010Assignee: General Electric CompanyInventors: Zachary Matthew Stum, Kevin Sean Matocha, Jody Alan Fronheiser, Ljubisa Dragoljub Stevanovic
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Publication number: 20090267141Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: ApplicationFiled: July 7, 2009Publication date: October 29, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum
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Publication number: 20090242901Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.Type: ApplicationFiled: June 12, 2009Publication date: October 1, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Gregory Keith Dudoff, William Gregg Hawkins, Zachary Matthew Stum, Stephen Daley Arthur, Dale Marius Brown
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Patent number: 7595241Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: GrantFiled: August 23, 2006Date of Patent: September 29, 2009Assignee: General Electric CompanyInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum
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Publication number: 20090194772Abstract: A method of forming a vertical MOSFET device includes forming a first trench within a semiconductor layer of a first polarity, the first trench generally defining a well region of a second polarity opposite the first polarity; growing a first epitaxial well layer of the second polarity over the original semiconductor layer; growing a second epitaxial source contact layer of the first polarity over the well layer; forming a second trench through the source contact layer and at least a portion of the well layer; growing a third epitaxial layer of the second polarity over the source contact layer; and planarizing at least the first and second epitaxial layers so as to expose an upper surface of the original semiconductor layer, wherein a top surface of the third epitaxial layer is substantially coplanar with a top surface of the source contact layer prior to ohmic contact formation.Type: ApplicationFiled: January 31, 2008Publication date: August 6, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Zachary Matthew Stum, Kevin Sean Matocha, Jody Alan Fronheiser, Ljubisa Dragoljub Stevanovic
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Publication number: 20090159896Abstract: A method of making a silicon carbide MOSFET is disclosed. The method includes providing a semiconductor device structure, wherein the device structure comprises a silicon carbide semiconductor device layer, an ion implanted well region of a first conductivity type formed in the semiconductor device layer, an ion implanted source region of a second conductivity type formed into the ion implanted well region; providing a mask layer over the semiconductor device layer, the mask layer exposing a portion of the ion implanted source region, then etching through the portion of the ion implanted source region to form a dimple; then implanting ions through the dimple to form a high dopant concentration first conductivity type ion implanted contact region, wherein the ion implanted contact region is deeper than the ion implanted well region; then removing the contact region mask layer and annealing implanted ions.Type: ApplicationFiled: December 20, 2007Publication date: June 25, 2009Applicant: GENERAL ELECTRIC COMPANYInventors: Stephen Daley Arthur, Kevin Sean Matocha, Zachary Matthew Stum, Jesse Berkley Tucker
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Publication number: 20080146004Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.Type: ApplicationFiled: December 13, 2006Publication date: June 19, 2008Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Vinayak Tilak, Stephen Daley Arthur, Zachary Matthew Stum
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Publication number: 20080132047Abstract: A method for doping impurities into a device layer is provided. The method includes providing a carbonized dopant layer over a device layer, wherein the carbonized dopant layer comprises one or more dopant impurities, and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.Type: ApplicationFiled: December 5, 2006Publication date: June 5, 2008Applicant: GENERAL ELECTRIC COMPANYInventors: Greg Thomas Dunne, Jesse Berkley Tucker, Stanislav Ivanovich Soloviev, Zachary Matthew Stum
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Publication number: 20080050876Abstract: A method of forming a vertical MOSFET device includes forming a trench within a drift layer substrate, the drift layer comprising a first polarity type, the trench generally defining a well region of a second polarity type opposite the first polarity type. An ohmic contact layer is formed within a bottom surface of the trench, the ohmic contact layer comprising a material of the second polarity type. A layer of the second polarity type is epitaxially grown over the drift layer, sidewall surfaces of the trench, and the ohmic contact layer. A layer of the first polarity type is epitaxially grown over the epitaxially grown layer of the second polarity type so as to refill the trench, and the epitaxially grown layers of the first and second polarity type are planarized so as to expose an upper surface of the drift layer substrate.Type: ApplicationFiled: August 23, 2006Publication date: February 28, 2008Applicant: GENERAL ELECTRIC COMPANYInventors: Kevin Sean Matocha, Jody Alan Fronheiser, Larry Burton Rowland, Jesse Berkley Tucker, Stephen Daley Arthur, Zachary Matthew Stum