Patents by Inventor Zack Waters
Zack Waters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11978155Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.Type: GrantFiled: September 25, 2020Date of Patent: May 7, 2024Assignee: Intel CorporationInventors: Selvakumar Panneer, Mrutunjayya Mrutunjayya, Carl S. Marshall, Ravishankar Iyer, Zack Waters
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Patent number: 11710269Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: GrantFiled: July 28, 2022Date of Patent: July 25, 2023Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
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Publication number: 20230186545Abstract: Described herein is a cloud-based gaming system in which multiple views of a spectated E-sports event can be rendered and combined into an immersive video having at least three degrees of freedom. Low-latency generation of the immersive video is facilitated via the use of GPU-controlled non-volatile memory on which rendered data for multiple viewpoints are stored.Type: ApplicationFiled: December 15, 2021Publication date: June 15, 2023Applicant: Intel CorporationInventors: Travis Schluessler, Zack Waters, Charles Moidel, Michael Apodaca, Murali Ramadoss, Rajabali Koduri
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Publication number: 20220366630Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Applicant: Intel CorporationInventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, DANIEL JOHNSTON, JASON SURPRISE, PRASOONKUMAR SURTI, SUBRAMANIAM MAIYURAN, PETER DOYLE, SAURABH SHARMA, ANKUR SHAH, MURALI RAMADOSS
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Patent number: 11443406Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.Type: GrantFiled: May 18, 2021Date of Patent: September 13, 2022Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Charles Moidel, Michael Apodaca, Murali Ramadoss
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Patent number: 11403805Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: GrantFiled: May 3, 2021Date of Patent: August 2, 2022Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
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Publication number: 20220101597Abstract: An apparatus to facilitate inferred object shading is disclosed. The apparatus comprises one or more processors to receive rasterized pixel data and hierarchical data associated with one or more objects and perform an inferred shading operation on the rasterized pixel data, including using one or more trained neural networks to perform texture and lighting on the rasterized pixel data to generate a pixel output, wherein the one or more trained neural networks uses the hierarchical data to learn a three-dimensional (3D) geometry, latent space and representation of the one or more objects.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Selvakumar Panneer, Mrutunjayya Mrutunjayya, Carl S. Marshall, Ravishankar Iyer, Zack Waters
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Publication number: 20210304351Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.Type: ApplicationFiled: May 18, 2021Publication date: September 30, 2021Applicant: Intel CorporationInventors: Travis Schluessler, Zack Waters, Charles Moidel, Michael Apodaca, Murali Ramadoss
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Publication number: 20210272349Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: ApplicationFiled: May 3, 2021Publication date: September 2, 2021Applicant: Intel CorporationInventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, DANIEL JOHNSTON, JASON SURPRISE, PRASOONKUMAR SURTI, SUBRAMANIAM MAIYURAN, PETER DOYLE, SAURABH SHARMA, ANKUR SHAH, MURALI RAMADOSS
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Patent number: 11037269Abstract: Described herein are devices, systems and methods to utilize non-volatile memory to save and retrieve data that is used to accelerate the load and resume of GPU accelerated applications. Non-volatile memory and GPU logic are configured to enable the GPU to directly access the non-volatile memory to enable data to be read without requiring the data to traverse the CPU and CPU memory. This data access path creates a faster method for loading data into GPU local memory.Type: GrantFiled: March 27, 2020Date of Patent: June 15, 2021Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Charles Moidel, Michael Apodaca, Murali Ramadoss
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Patent number: 10997771Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: GrantFiled: August 29, 2018Date of Patent: May 4, 2021Assignee: Intel CorporationInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Daniel Johnston, Jason Surprise, Prasoonkumar Surti, Subramaniam Maiyuran, Peter Doyle, Saurabh Sharma, Ankur Shah, Murali Ramadoss
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Patent number: 10733692Abstract: Apparatus and method for resilient interface for updating a graphics processor.Type: GrantFiled: November 9, 2018Date of Patent: August 4, 2020Assignee: Intel CorporationInventors: Slawomir Grajewski, Jason Surprise, Zack Waters, Mike Apodaca
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Patent number: 10733693Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.Type: GrantFiled: December 4, 2018Date of Patent: August 4, 2020Assignee: INTEL CORPORATIONInventors: Travis Schluessler, Zack Waters, Michael Apodaca, Jason Surprise, Peter Doyle
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Publication number: 20200175643Abstract: Embodiments described herein provide data processing device comprising a processor, a memory, and a large draw monitor comprising a processing unit to determine whether a vertex count for a graphics workload exceeds a threshold value, and in response to a determination that the vertex count for the graphics workload exceeds the threshold value, to divide the graphics workload over graphics processing units instantiated on multiple separate tiles. Other embodiments may be described and claimed.Type: ApplicationFiled: December 4, 2018Publication date: June 4, 2020Applicant: Intel CorporationInventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, JASON SURPRISE, PETER DOYLE
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Publication number: 20200151845Abstract: Apparatus and method for resilient interface for updating a graphics processor.Type: ApplicationFiled: November 9, 2018Publication date: May 14, 2020Inventors: SLAWOMIR GRAJEWSKI, JASON SURPRISE, ZACK WATERS, MIKE APODACA
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Publication number: 20200074713Abstract: Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.Type: ApplicationFiled: August 29, 2018Publication date: March 5, 2020Inventors: TRAVIS SCHLUESSLER, ZACK WATERS, MICHAEL APODACA, DANIEL JOHNSTON, JASON SURPRISE, PRASOONKUMAR SURTI, SUBRAMANIAM MAIYURAN, PETER DOYLE, SAURABH SHARMA, ANKUR SHAH, MURALI RAMADOSS
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Publication number: 20070244663Abstract: A software or hardware test system and method repeatedly obtains testing status of a plurality of test units in a group while the test units are testing hardware or software being executed on the test units. The system and method provides for display of the current testing status of the plurality of units of the group while the plurality of test units is performing software testing. In another embodiment, a test system and method compiles heuristic data for a plurality of test units that are assigned to one or more groups of test units. The heuristic data may include, for example, data representing a frequency of use on a per-test unit basis over a period of time, and other heuristic data. The test system and method evaluates job queue sizes on a per-group basis to determine whether there are under-utilized test units in the group and determines on a per-group of test unit basis whether a first group allows for dynamic reassignment of a test unit in the group based on at least the compiled heuristic data.Type: ApplicationFiled: April 12, 2006Publication date: October 18, 2007Applicant: ATI Technologies Inc.Inventors: Nicholas Haemel, Zack Waters