Patents by Inventor Zaheed Sadrudin Karim

Zaheed Sadrudin Karim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6638847
    Abstract: A method of forming solder bumps on a chip or wafer for flip-chip applications comprises the steps of providing a chip or wafer having a plurality of metal bonds pads which provide electrical connection to the chip or wafer, and applying a solder bump comprising pure tin or a tin alloy selected from tin-copper, tin-silver, tin-bismuth or tin-silver-copper by an electroplating technique, and melting the solder bumps by heating to a temperature above the bump melting point to effect reflow.
    Type: Grant
    Filed: April 19, 2000
    Date of Patent: October 28, 2003
    Assignee: Advanced Interconnect Technology Ltd.
    Inventors: Edwin Wai Ming Cheung, Zaheed Sadrudin Karim
  • Patent number: 6501185
    Abstract: A semiconductor wafer having solder bumps thereon for use in flip-chip bonded integrated circuits comprises a semiconductor substrate formed with metal bond pads at selected locations thereon, a metal electroplating buss layer or layers over the bond pads, a layer of solder-wettable under bump metal on the buss layer, a layer of barrier metal which overlies and encapsulates the solder-wettable metal, and a solder bump formed on the barrier metal.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: December 31, 2002
    Assignee: Advanced Interconnect Technology Ltd.
    Inventors: Yeung Ming Chow, Zaheed Sadrudin Karim
  • Publication number: 20020185733
    Abstract: A semiconductor wafer having solder bumps thereon for use in flip-chip bonded integrated circuits comprises a semiconductor substrate formed with metal bond pads at selected locations thereon, a metal electroplating buss layer or layers over the bond pads, a layer of solder-wettable under bump metal on the buss layer, a layer of barrier metal which overlies and encapsulates the solder-wettable metal, and a solder bump formed on the barrier metal.
    Type: Application
    Filed: May 28, 2002
    Publication date: December 12, 2002
    Inventors: Yeung Ming Chow, Zaheed Sadrudin Karim
  • Patent number: 6413851
    Abstract: A method of fabrication of solder bumps on a semiconductor wafer provided with metal bond pads comprises the steps of: (a) applying a metal adhesion/barrier/electroplating buss layer or layers on at least the bond pads; (b) forming a layer of a resist in a predefined pattern defining openings therein over the bond pads; (c) applying a layer of solder-wettable under bump metal into the openings; (d) removing a volume of resist from the regions of the openings to create an opening between an edge of the layer of wettable metal and the resist; (e) applying a layer of a barrier metal over the layer of solder-wettable metal including the openings created at step (d) while encapsulates the layer of wettable metal; (f) fabricating a solder bump onto the layer of barrier metal; and (g) removing the resist material; and (h) removing any exposed adhesion/barrier layer.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: July 2, 2002
    Assignee: Advanced Interconnect Technology, Ltd.
    Inventors: Yeung Ming Chow, Zaheed Sadrudin Karim