Patents by Inventor Zaher Baidas

Zaher Baidas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11126218
    Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 21, 2021
    Assignee: Integrated Device Technology, Inc.
    Inventors: Zaher Baidas, Ernst JG den Broeder, Leonid Goldin
  • Publication number: 20200033910
    Abstract: A system that switches between a clock signal from a first line card and a clock signal from a second line card based on information transmitted from the first line card and the second line card on timing signals is presented. Some methods include receiving a first pulse-width modulated clock signal from a first line card, the first pulse-width modulated clock signal including information regarding the status of the first line card; receiving a second pulse-width modulated clock signal from a second line card, the second pulse-width modulated clock signal including information regarding the status of the second line card; producing a clock signal from the first pulse-width modulated clock signal; and switching to producing the clock signal from the second pulse-width modulated clock signal based on the information in the first pulse-width modulated clock signal.
    Type: Application
    Filed: July 24, 2019
    Publication date: January 30, 2020
    Inventors: Zaher Baidas, Ernst JG den Broeder, Leonid Goldin
  • Patent number: 10075284
    Abstract: A system and method for clock phase alignment at a plurality of line cards over a backplane of a communication system. Phase adjustments are continually made for the clock signals at the line cards by dynamically measuring the propagation delay between the timing device and each of the plurality of line cards and continuously communicating the appropriate phase adjustment to each of the plurality of line cards.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: September 11, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Silvana Rodrigues, Michael Rupert, Zaher Baidas, Leon Goldin
  • Patent number: 9628255
    Abstract: A method of operating a clock circuit can include transmitting a clock signal from a transmitter of a first system to a receiver of a second system, where a first repeating edge of a clock cycle of the clock signal repeats at a predetermined constant frequency within the clock signal to synchronize operations of the second system, and varying, by the first system, a second edge within the clock cycle of the clock signal to transmit a data transmission within the clock signal.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: April 18, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Zaher Baidas, Bogdan Staicu, Menno Tjeerd Spijker
  • Patent number: 9479182
    Abstract: A method of synchronizing operations between integrated circuits can include transmitting a first clock signal from a first transmitter associated with a first integrated circuit of a first system, to a receiver associated with a second integrated circuit of a second system, receiving a second clock signal from a second transmitter associated with a third integrated circuit of the second system, receiving at the first system a first phase difference determined by the second system, wherein the first phase difference is determined between the first clock signal at the second system and the second clock signal at the second system, determining a second phase difference at the first system, wherein the second phase difference is determined between the first clock signal at the first system and the second clock signal at the first system, and determining a difference between the first phase difference and the second phase difference.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: October 25, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Zaher Baidas, Bogdan Staicu, Menno Tjeerd Spijker
  • Patent number: 7843954
    Abstract: A telephone subscriber line device for providing an interface between a legacy telephone circuit based on circuit-switched technology and a packet network has a legacy interface for connection to telephone circuit; a packet interface for connection to a packet network, processing circuitry for converting between legacy telephone signals and packet signals, and a cascadable expansion bus permitting multiple said devices to be connected to a common port on a packet network. Such a device is highly scalable.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: November 30, 2010
    Assignee: Zarlink Semiconductor Inc.
    Inventors: Gordon J. Reesor, Zaher Baidas, Paul Nicholas
  • Publication number: 20090154484
    Abstract: A telephone subscriber line device for providing an interface between a legacy telephone circuit based on circuit-switched technology and a packet network has a legacy interface for connection to telephone circuit; a packet interface for connection to a packet network, processing circuitry for converting between legacy telephone signals and packet signals, and a cascadable expansion bus permitting multiple said devices to be connected to a common port on a packet network. Such a device is highly scalable.
    Type: Application
    Filed: December 11, 2008
    Publication date: June 18, 2009
    Applicant: ZARLINK SEMICONDUCTOR INC.
    Inventors: Gordon J. Reesor, Zaher Baidas, Paul Nicholas