Abstract: Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M×N and an n×n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n×n block and to one block contained within the M×N pixel block and horizontally offset within the n×n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n×n pixel block and to one block contained within an M×N block and horizontally offset within the n×n block. M, N, and n are integers.

Abstract: Provided are electron emitters based upon diamondoid monolayers, preferably self-assembled higher diamondoid monolayers. High intensity electron emission has been demonstrated employing such diamondoid monolayers, particularly when the monolayers are comprised of higher diamondoids. The application of such diamondoid monolayers can alter the band structure of substrates, as well as emit monochromatic electrons, and the high intensity electron emissions can also greatly improve the efficiency of field-effect electron emitters as applied to industrial and commercial applications.

Abstract: An exemplary graphics processing unit (GPU) comprises a decoder and a video processing unit. The decoder is configured to decode a first and a second deblocking filter acceleration instruction. The first and second deblocking filter instructions are associated with a deblocking filter used by a particular video decoder. The video processing unit is configured to receive encoded by the deblocking filter acceleration instructions, and to determine first and second memory sources specified by the received parameters as one of a plurality of memory sources located on the GPU. The video processing unit is further configured to load a first block of pixel data from the first memory source, and to apply the deblocking filter to the first block of pixel data, and to load a second block of pixel data from the second memory source, and to apply the deblocking filter to the second block of pixel data.

Abstract: We disclose the isolation and characterization of sirtuin 1 [SIRT1] splice variants.

Abstract: A thin film evaporator has a shell with tubes extending through the shell in at least one pass. The shell has a top and a bottom. Process fluid flows through the tubes. A suction from a compressor is applied to the top of the shell at a refrigerant outlet. Refrigerant is introduced into the shell at the bottom and is distributed across the bottom region of the shell. The refrigerant flows up and contacts the tubes, exchanging heat therewith before flowing out of the shell top. Oil in the refrigerant contacts the shell wall and drains into a sump.

Abstract: Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a plurality of instructions and a graphics processing unit. The graphics processing unit is configured to process the instructions according to a multi-stage scalar pipeline and store condition code values in the branch control stack. The graphics processing unit is further configured to process branch instructions using condition code values stored in the condition register at the top of the branch control stack.

Abstract: Provided are electron emitters based upon diamondoid monolayers, preferably self-assembled higher diamondoid monolayers. High intensity electron emission has been demonstrated employing such diamondoid monolayers, particularly when the monolayers are comprised of higher diamondoids. The application of such diamondoid monolayers can alter the band structure of substrates, as well as emit monochromatic electrons, and the high intensity electron emissions can also greatly improve the efficiency of field-effect electron emitters as applied to industrial and commercial applications.

Abstract: Methods and systems are provided for steering network packets. According to one embodiment, a dynamically configurable steering table is stored within a memory of each network interface of a networking routing/switching device. The steering table represents a mapping that logically assigns each of the network interfaces to one of multiple packet processing resources of the network routing/switching device. The steering table has contained therein information indicative of a unique identifier/address of the assigned packet processing resource. Responsive to receiving a packet on a network interface, the network interface performs Layer 1 or Layer 2 steering of the received packet to the assigned packet processing resource by retrieving the information indicative of the unique identifier/address of the assigned packet processing resource from the steering table based on a channel identifier associated with the received packet and the received packet is processed by the assigned packet processing resource.

Abstract: Methods and systems for providing IP services in an integrated fashion are provided. According to one embodiment, a load associated with multiple virtual routing processing resources of an IP service generator of a virtual router (VR) based switch is monitored. Packets are load balanced among the virtual routing processing resources. A packet flow cache is maintained with packet flow entries containing information indicative of packet processing actions for established packet flows. Deep packet classification is performed to determine whether a packet is associated with an established packet flow. If so, the packet is directed to one of multiple virtual services processing resources representing application-tailored engines configured to provide network-based IP services including one or more of virtual private network (VPN) processing, firewall processing, Uniform Resource Locator (URL) filtering and anti-virus processing.

Abstract: Methods and systems are provided for routing traffic through a virtual router-based network switch. According to one embodiment, a flow data structure is established that identifies current packet flows associated with multiple virtual routers in the virtual router-based network device. When an incoming packet is received by the virtual router-based network device, it is then determined whether the incoming packet is associated with a current packet flow by accessing the flow data structure based on a header associated with the incoming packet. If it is determined that the incoming packet is associated with the current packet flow, then the incoming packet is hardware forwarded via a network interface of the virtual router-based network device without intervention by a processor of the virtual router-based network device, otherwise the incoming packet is forwarded to software on the processor for flow learning.

Abstract: Methods and systems are provided for steering network packets. According to one embodiment, a mapping associates a processing resource with a network interface module (netmod) and/or a number of line interface ports included within the netmod. In one embodiment, the mapping is configurable within the processing resource and pushed to the netmod. The netmod uses the mapping to steer network packets to the processing resource when the packets conform to the mapping. The mapping may be additionally used to identify a specific process that is to be performed against the packets once the processing resource receives the steered packets from the netmod.

Abstract: Methods and systems for providing IP services in an integrated fashion are provided. According to one embodiment, a system includes a switch fabric and a line interface/network module, multiple virtual routing engines (VREs) and a virtual services engine (VSE) coupled with the switch fabric. The line interface/network module receives packets, steers ingress packets to a selected VRE and transmits egress packets according to their relative priority. VREs determines if a packet associated with a packet flow requires processing by the VSE by performing flow-based packet classification on the packet and evaluating forwarding state information associated with previously stored flow learning results. The VSE includes a central processing unit configured to perform firewall processing, Uniform Resource Locator (URL) filtering and anti-virus processing. If the packet is determined to require processing by the VSE, then the packet is steered to the VSE for firewall, URL filtering and/or anti-virus processing.

Abstract: Compounds of the formula are disclosed as Mnk2 inhibitors which are useful for the treatment and prevention of metabolic disorders such as obesity and diabetes.

Abstract: Methods and systems are provided for hardware-accelerated packet multicasting in a virtual routing system. According to one embodiment, a virtual routing engine (VRE) including virtual routing processors and corresponding memory systems are provided. The VRE implements virtual routers (VRs) operable on the virtual routing processors and associated routing contexts utilizing potentially overlapping multicast address spaces resident in the memory systems. Multicasting of multicast flows originated by subscribers of a service provider is simultaneously performed on behalf of the subscribers. A VR is selected to handle multicast packets associated with a multicast flow. A routing context of the VRE is switched to one associated with the VR. A packet of the multicast flow is forwarded to multiple destinations by reading a portion of the packet from a common buffer for each instance of multicasting and applying transform control instructions to the packet for each instance of multicasting.

Abstract: Compounds of the formula wherein R1 represents optionally substituted C1-C10 alkyl, aryl or heteroaryl, and R3 represents alkoxy-substituted aryl or optionally substituted heteroaryl, are disclosed as Mnk2 inhibitors which are useful for the treatment and prevention of metabolic disorders such as obesity and diabetes.

Abstract: Methods and systems are provided for hardware-accelerated packet multicasting in a virtual routing system. According to one embodiment, a multicast packet is received at an ingress system of a packet-forwarding engine (PFE). The ingress system identifies flow classification indices for the multicast packet. Then, for each instance of multicasting, the ingress system sends a single copy of the multicast packet and the flow classification indices to an egress system of the PFE. The single copy of the multicast packet is buffered in a memory accessible by the egress system. The egress system prepares the multicast packet for transmission by for each flow classification index, identifying corresponding transform control instructions based on the flow classification index, reading the single copy of the multicast packet from the memory, causing the multicast packet to be transformed in accordance with the identified transform control instructions and outputting the transformed multicast packet.

Abstract: Embodiments of exponent processing systems and methods are disclosed. One method embodiment, among others, comprises performing a first table lookup using a first address to provide a first value corresponding to the first component part, setting an integer exponent to provide an integer-based value corresponding to the integer component, performing a second table lookup using a second and third address to provide a second value and a third value corresponding to the second component part and the third component part, respectively, expanding and normalizing the second and third values to provide expanded and normalized second and third values, combining the expanded and normalized second and third values to produce a first product, and computing the exponential function by combining the first value, the integer-based value, and the first product.

Abstract: A processor and a method for executing VLIW instructions by first fetching a VLIW instruction and then identifying from option bits encoded in a first one of the instructions within the fetched VLIW instruction packet which, if any, of the remaining instructions within the VLIW instruction are to be executed in the same execution cycle as the first instruction. Finally, executing the first instruction and any remaining instructions identified from the encoded option bits.

Abstract: An intra-frame prediction method and a prediction apparatus using the same are provided. The prediction apparatus includes an input data unit, a control unit, an selection unit, a processing unit, and an output data selecting unit. The input data unit provides surroundings pixels of a predicted block. The control unit provides an input selection signal, a computing parameter, and an output selection signal. The selection unit selects the surroundings pixels according to the input selection signal. The processing unit computes the selected surroundings pixels for producing a plurality of results according to the computing signal. The output data unit selects results according to the output selection signal.

Abstract: Methods and systems for providing IP services in an integrated fashion are provided. According to one embodiment, a system includes a switch fabric and a line interface/network module, multiple virtual routing engines (VREs) and a virtual services engine (VSE) coupled with the switch fabric. The line interface/network module receives packets, steers ingress packets to a selected VRE and transmits egress packets according to their relative priority. VREs determines if a packet associated with a packet flow requires processing by the VSE by performing flow-based packet classification on the packet and evaluating forwarding state information associated with previously stored flow learning results. The VSE includes a central processing unit configured to perform firewall processing, Uniform Resource Locator (URL) filtering and anti-virus processing. If the packet is determined to require processing by the VSE, then the packet is steered to the VSE for firewall, URL filtering and/or anti-virus processing.