Abstract: Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.

Abstract: Programmable integrated circuits with configurable logic circuitry and routing resources are provided. Portions of the routing resources on a programmable integrated circuit may be used in implementing a desired user-specified custom logic function, whereas other portions of the routing resources on the programmable integrated circuit may be unused. The unused routing resources may include adjacent pairs of routing paths. These paths may be coupled to control circuitry configured to drive the routing paths to desired voltage levels to provide an optimal amount of decoupling capacitance. In one suitable arrangement, two adjacent routing paths may both be driven to a positive power supply voltage level. In another suitable arrangement, the two adjacent routing paths may be driven to the positive power supply voltage level and a ground power supply voltage level, respectively.

Abstract: A method for performing static timing analysis includes generating current source driver models for components in a system operating at a supply voltage during a simulation of a path. A delay value for the path is derived from the simulation using the current source driver models for components along the path.

Abstract: A method for designing a system on a field programmable gate array (FPGA) includes routing one or more booster wires alongside an interconnect to reduce a delay of a signal being transmitted on the interconnect. According to one aspect of the present invention, the routing of the one or more booster wires is performed in response to determining that a timing requirement of the system has not been met.

Abstract: A logic design system is provided for designing programmable logic device integrated circuits with minimized predriver power consumption. The logic design system identifies predriver circuits that can operate satisfactorily at reduced predriver power supply levels. One or more reduced predriver power supply levels for powering the predriver circuits are identified by the logic design system. The predriver power supply levels that are identified can be different than a maximum allowable power supply voltage used for powering input-output circuitry on the programmable logic device integrated circuit. There may be multiple blocks of predriver circuitry, each of which is powered using a potentially different predriver power supply voltage. The logic design system uses on-screen options to accept user-supplied settings related to minimizing predriver power consumption.