Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.

Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.

Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.

Abstract: Various embodiments are described of a system for improved processor instructions for a software-configurable processing element. In particular, various embodiments are described which accelerate functions useful for FEC encoding and decoding. In particular, the processing element may be configured to implement one or more instances of the relevant functions in response to receiving one of the processor instructions. The processing element may later be reconfigured to implement a different function in response to receiving a different one of the processor instructions. Each of the disclosed processor instructions may be implemented repeatedly by the processing element to repeatedly perform one or more instances of the relevant functions with a throughput approaching one or more solutions per clock cycle.

Abstract: Various embodiments are described of a system and method for improved SCL decoder operation. In particular, various embodiments are described which improve the efficiency of the buffer management based on updated path metric statistics. In some embodiments, the SCL decoder may perform selective replacement to limit the extent of LLR updates per row only to the statistics that have changed since the previous update cycle. In some embodiments, the SCL decoder may perform deferred updates, which may involves in-place calculation of both û?=0 and û?=1 bit estimate (LLR) updates based on the row from which the updated row will be derived.

Abstract: Method and apparatus for signal detection in dynamic channels with high carrier frequency offset are provided. A coherent detector and a non-coherent detector are operated in parallel on a block of samples of an input signal to determine respective time offset candidates of the input signal. The time offset candidate obtained from the non-coherent detector is used to determine a frequency offset candidate of the input signal.

Abstract: A method and apparatus for automatic frequency control in a receiver of a wireless device, the method determining a channel estimation for a received signal; calculating a signal to noise ratio for the channel estimation; applying a weighting factor determined based on the calculated signal to noise ratio for the channel estimation to the channel estimation to create a weighted channel estimation; and supplying the weighted channel estimation to a voltage controlled oscillator.

Abstract: A method and apparatus for automatic frequency control in a receiver of a wireless device, the method determining a channel estimation for a received signal; calculating a signal to noise ratio for the channel estimation; applying a weighting factor determined based on the calculated signal to noise ratio for the channel estimation to the channel estimation to create a weighted channel estimation; and supplying the weighted channel estimation to a voltage controlled oscillator.

Abstract: A method and apparatus for automatic frequency control in a receiver of a wireless device, the method determining a channel estimation for a received signal; calculating a signal to noise ratio for the channel estimation; applying a weighting factor determined based on the calculated signal to noise ratio for the channel estimation to the channel estimation to create a weighted channel estimation; and supplying the weighted channel estimation to a voltage controlled oscillator.

Abstract: A method and apparatus for automatic frequency control in a receiver of a wireless device, the method determining a channel estimation for a received signal; calculating a signal to noise ratio for the channel estimation; applying a weighting factor determined based on the calculated signal to noise ratio for the channel estimation to the channel estimation to create a weighted channel estimation; and supplying the weighted channel estimation to a voltage controlled oscillator.