Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Abstract: A system and method for a computing tile of a multi-tiled integrated circuit includes a plurality of distinct tile computing circuits, wherein each of the plurality of distinct tile computing circuits is configured to receive fixed-length instructions; a token-informed task scheduler that: tracks one or more of a plurality of distinct tokens emitted by one or more of the plurality of distinct tile computing circuits; and selects a distinct computation task of a plurality of distinct computation tasks based on the tracking; and a work queue buffer that: contains a plurality of distinct fixed-length instructions, wherein each one of the fixed-length instructions is associated with one of the plurality of distinct computation tasks; and transmits one of the plurality of distinct fixed-length instructions to one or more of the plurality of distinct tile computing circuits based on the selection of the distinct computation task by the token-informed task scheduler.

Abstract: Systems and methods for analyzing performance of a processing system are based on performance counters provided in trace points located at selected nodes of the processing system. A first transaction to be monitored is identified as a transaction to be monitored at a first trace point if the transaction is detected, by a performance counter, more than a threshold number of times at the first trace point. A first trace tag identifier is associated with the first transaction at the first trace point. The first transaction is identified at one or more other trace points based on the first trace tag identifier. Based on time stamps at which the first transaction is identified at the trace points, information such as trace information, latency, locality of a consuming device of the first transaction, etc. is obtained from the various trace points.

Abstract: Systems and methods for analyzing performance of a processing system are based on performance counters provided in trace points located at selected nodes of the processing system. A first transaction to be monitored is identified as a transaction to be monitored at a first trace point if the transaction is detected, by a performance counter, more than a threshold number of times at the first trace point. A first trace tag identifier is associated with the first transaction at the first trace point. The first transaction is identified at one or more other trace points based on the first trace tag identifier. Based on time stamps at which the first transaction is identified at the trace points, information such as trace information, latency, locality of a consuming device of the first transaction, etc. is obtained from the various trace points.