Patents by Inventor Zainulabedin J. Aurangabadwala

Zainulabedin J. Aurangabadwala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Minimizing snoop traffic locally and across cores on a chip multi-core fabric
    Patent number: 10102129
    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: October 16, 2018
    Assignee: Intel Corporation
    Inventors: Krishna N. Vinod, Avinash Sodani, Zainulabedin J. Aurangabadwala
  • MINIMIZING SNOOP TRAFFIC LOCALLY AND ACROSS CORES ON A CHIP MULTI-CORE FABRIC
    Publication number: 20170177483
    Abstract: A processor includes a processing core, a L1 cache comprising a first processing core and a first L1 cache comprising a first L1 cache data entry of a plurality of L1 cache data entries to store data. The processor also includes an L2 cache comprising a first L2 cache data entry of a plurality of L2 cache data entries. The first L2 cache data entry corresponds to the first L1 cache data entry and each of the plurality of L2 cache data entries are associated with a corresponding presence bit (pbit) of a plurality of pbits. Each of the plurality of pbits indicates a status of a corresponding one of the plurality of L2 cache data entries. The processor also includes a cache controller, which in response to a first request among a plurality of requests to access the data at the first L1 cache data entry, determines that a copy of the data is stored in the first L2 cache data entry; and retrieves the copy of the data from the L2 cache data entry in view of the status of the pbit.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: Krishna N. Vinod, Avinash Sodani, Zainulabedin J. Aurangabadwala