Abstract: A strain of Bifidobacterium longum subsp. infantis Y46 with fimbriae (BI_Y46) includes a unique flagella structure, exhibits strong abilities in utilizing 2-fucosyllactose (2?-FL), galacto-oligosaccharides and short-chain galacto-oligosaccharides, possesses excellent probiotic characteristics with higher levels of extracellular polysaccharides and surface proteins than a strain of Bifidobacterium longum subsp. infantis M63 (BI_M63) and a strain of Bifidobacterium longum subsp. infantis ATCC 15697 (BI_15697), and further displays stronger ability to tolerate gastric acid and inhibitory ability of the cell-free supernatant to Escherichia coli ATCC 15922 than the BI_15697. Therefore, the BI_Y46 has excellent probiotic potential and can be used to develop probiotics, infant food, prebiotic products, and functional foods.

Abstract: A ship cabin loading capacity measurement method and apparatus thereof, comprises: acquiring point cloud measurement data of a ship cabin; optimizing the point cloud measurement data according to a predetermined point cloud data processing rule, and generating optimized ship cabin point cloud data; calculating said ship cabin point cloud data with a predetermined loading capacity calculation rule, and getting ship cabin loading capacity data. According to the ship cabin loading capacity measurement method of the present invention, the point cloud measurement data can be acquired by a lidar, and processing the point cloud measurement data of the ship cabin with a predetermined point cloud data processing law and a computation law, and as the point cloud data processing law and the computation law can be deployed in a computer device in advance, after point cloud measurement data acquisition, loading capacity of a ship cabin can be acquired quickly and precisely.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: An image sensor chip includes a structural layer member including a plurality of structural layers. Each of the plurality of structural layers is distributed in a photosensitive circuit area and a peripheral reading circuit area of the image sensor chip. A first part and a second part of one structural layer in the structural layer member include insulation materials with different characteristic properties. The first part is a part of the one structural layer in the photosensitive circuit area, and the second part is a part of the one structural layer in the peripheral reading circuit area.

Abstract: A pixel includes a photoelectric converter, a transfer transistor, a reset transistor, a first source follower, a second source follower, and a switch device. A gate of the first source follower and a gate of the second source follower are electrically connected to a floating diffusion region between the transfer transistor and the reset transistor, and a source of the first source follower and a source of the second source follower are connected to a row selection line via a select transistor. The switch device is connected to the second source follower and used to be turned on to allow the second source follower to work simultaneously with the first source follower, or to be turned off to allow the first source follower to work while the second source follower does not work.

Abstract: An image sensor includes a photo-sensing circuit region, a peripheral circuit region, and a light-blocking structure. The photo-sensing circuit region is formed in a semiconductor wafer and includes a plurality of photo-sensing devices. The peripheral circuit region is formed in the semiconductor wafer. The light-blocking structure is disposed between one or more of the plurality of photo-sensing devices and the peripheral circuit region. The light-blocking structure is configured to block at least a portion of light from reaching the one or more of the plurality of the photo-sensing devices, where the stray light comes from the peripheral circuit region. The light-blocking structure includes a material different from a material of the semiconductor wafer.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A backside illumination image sensor and a method for reducing a dark current of the backside illumination image sensor. The backside illumination image sensor comprises: a photodiode, a first conductive type isolated layer (120); a gate structure of a pass transistor, corresponding to the first conductive type isolated layer (120) and formed on an upper surface of a first conductive type semiconductor substrate (100), the gate structure (130) comprising: gate oxide (131), a gate layer (132), and a gate sidewall (133), and the gate structure (130) correspondingly covering the photodiode; and a floating diffusion zone (140), formed in the first conductive type semiconductor substrate (100) and having second conductive type heavy doping. In the backside illumination image sensor, a defect does not easily appear on a surface, right above the photodiode, of the first conductive type semiconductor substrate (100), so that a dark current is effectively prevented from being produced.

Abstract: An image sensor and a manufacturing method thereof are provided. The image sensor includes: a photo diode; a first-conductive-type isolating layer; a second-conductive-type lightly-doped region formed in the first-conductive-type semiconductor substrate; a first-conductive-type lightly-doped region formed under the second-conductive-type lightly-doped region, where the second-conductive-type lightly-doped region is isolated from the second-conductive-type region by the first-conductive-type lightly-doped region; a gate structure of a transfer transistor; and a floating diffusion region which is second-conductive-type heavily-doped.

Abstract: A backside illumination image sensor and a method for reducing a dark current of the backside illumination image sensor. The backside illumination image sensor comprises: a photodiode, a first conductive type isolated layer (120); a gate structure of a pass transistor, corresponding to the first conductive type isolated layer (120) and formed on an upper surface of a first conductive type semiconductor substrate (100), the gate structure (130) comprising: gate oxide (131), a gate layer (132), and a gate sidewall (133), and the gate structure (130) correspondingly covering the photodiode; and a floating diffusion zone (140), formed in the first conductive type semiconductor substrate (100) and having second conductive type heavy doping. In the backside illumination image sensor, a defect does not easily appear on a surface, right above the photodiode, of the first conductive type semiconductor substrate (100), so that a dark current is effectively prevented from being produced.

Abstract: An image sensor and a manufacturing method thereof are provided. The image sensor includes: a photo diode; a first-conductive-type isolating layer; a second-conductive-type lightly-doped region formed in the first-conductive-type semiconductor substrate; a first-conductive-type lightly-doped region formed under the second-conductive-type lightly-doped region, where the second-conductive-type lightly-doped region is isolated from the second-conductive-type region by the first-conductive-type lightly-doped region; a gate structure of a transfer transistor; and a floating diffusion region which is second-conductive-type heavily-doped.

Abstract: An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step.

Abstract: An internal gettering process for a Czochralski silicon wafers comprises: (1) heating a Cz silicon wafer to 1200-1250° C. at a heating rate of 50-100° C./s under a nitrogen atmosphere, maintaining for 30-150 seconds, cooling the Cz silicon wafer to 800-1000° C. first at a cooling rate of 5-50° C./s, and then cooling the Cz silicon wafer naturally; (2) annealing the Cz silicon wafer obtained in the step (1) at 800-900° C. under an argon atmosphere for a period of 8-16 hours. The present invention only involves two heat treatment steps which require lower temperature and shorter time comparing to the conventional processes. The density of the bulk microdefects and the width of the denuded zone can be easily controlled by the temperature, duration and cooling rate of rapid thermal processing in the first step.

Abstract: An assembly includes a main body, a screw, a nut and a restricting tab. The main body has a slot. A first end portion of the slot is narrower than a second end portion of the slot. The screw has a head and a shank. The shank is movable along the slot. The nut is threadedly engaged with the shank, and is wider than the first end portion and narrower than the second end portion. The restricting tab can be detachably sandwiched between the nut and the main body such that the shank can be trapped in the first end portion.